Plasma processing apparatus and plasma processing method

Patent metadata

Field	Value
Publication number	US-9711375-B2
Application number	US-201514626921-A
Country	US
Kind code	B2
Filing date	Feb 19, 2015
Priority date	Jun 24, 2014
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A plasma processing apparatus is provided including a processing chamber disposed within a vacuum vessel to form plasma therein, a processing stage disposed in the processing chamber to mount a wafer thereon, a first power supply for outputting an electric field supplied to form the plasma and forming an electric field of a first frequency supplied with repetition of a high output and a low output during processing of the wafer, a second power supply for supplying power of a second frequency to an electrode disposed within the processing stage, and a control device for causing a first value between load impedance at time of the high output of the electric field and load impedance at time of the low output of the electric field to match with impedance of the first power supply.

First claim

The invention claimed is:

1. A plasma processing apparatus comprising:
a processing chamber disposed within a vacuum vessel and depressurized inside to generate plasma therein;
a wafer stage disposed in the processing chamber to mount a wafer to be processed thereon;
a first power supply which is configured to supply first power of an electric field provided from over the vacuum vessel into the processing chamber to generate the plasma, the electric field being supplied in a first frequency with repetition of a high output and a low output during processing of the wafer;
a second power supply which is configured to supply second power of a second frequency to an electrode disposed within the wafer stage;
a first matching unit which is disposed on a feeding path of the first power from the first power supply to the vacuum vessel and which is configured to adjust impedance between the first power supply and the plasma in the processing chamber; and
a second matching unit which is disposed on a feeding path of the second power from the second power supply to the electrode of the wafer stage and which is configured to adjust an impedance between the second power supply and the plasma in the processing chamber,
wherein the first power supply is configured to be capable of changing the first power of the electric field, in the processing of the wafer, in values of the high output, the low output, and a ratio between a time period over which the first power is in the high output and a time period over which the first power is in the low output, respectively; and
wherein the first matching unit includes two adjustable capacitances; and a control device is configured to control the first power supply and the first matching unit to adjust the impedance between the first power supply and the plasma to a first value for first power by the two adjustable capacitances during the processing of the wafer, the first value of the impedance being determined between a load impedance at a time of the high output and at a time of the low output of the first power.

2. The plasma processing apparatus according to claim 1 , wherein the first value is determined depending upon the ratio of the first power.

3. The plasma processing apparatus according to claim 1 , wherein the first value is either load impedance in a case where the first power supply is in the high output or load impedance in a case where the first power supply is in the low output.

4. A plasma processing apparatus comprising:
a processing chamber disposed within a vacuum vessel and depressurized inside to generate plasma therein;
a wafer stage disposed in the processing chamber to mount a wafer to be processed thereon;
a first power supply which is configured to supply first power of an electric field provided from over the vacuum vessel into the processing chamber to generate the plasma;
a second power supply which is configured to supply second power of a second frequency to an electrode disposed within the wafer state, the second power of the second frequency being supplied with repetition of a high output and a low output during the processing of the wafer;
a first matching unit which is disposed on a feeding path of the first power from the first power supply to the vacuum vessel and which is configured to adjust impedance between the first power supply and the plasma in the processing chamber;
a second matching unit which is disposed on a feeding path of the second power from the second power supply to the electrode of the wafer stage and which is configured to adjust an impedance between the second power supply and the plasma in the processing chamber,
wherein the second power supply is configured to be capable of changing the second power of the second frequency, in the processing of the wafer, in values of the high output, the low output, and a duty ratio on periods thereof respectively, and
wherein the second matching unit includes two adjustable capacitances; and a control device is configured to control the second power supply and the second matching unit to adjust the impedance between the second power supply and the plasma to a second value by the two adjustable capacitances during the processing of the wafer, the second value of the impedance being determined between a load impedance at a time of the high output and a load impedance at a time of the low output of the second power.

5. The plasma processing apparatus according to claim 1 ,
wherein the second power supply is configured to supply the second power with repetition of a high output and a low output during the processing of the wafer and to be capable of changing the second power of the second frequency in values of the high output, the low output, and a duty ratio on periods thereof respectively, and
wherein the second matching unit includes two adjustable capacitances and is configured to adjust the impedance between the second power supply and the plasma to a second value by the two adjustable capacitances of the second matching unit during the processing of the wafer, the second value of the impedance being determined between a load impedance at a time of the high output and a load impedance at a time of the low output of the second power.

6. The plasma processing apparatus according to claim 5 , wherein the first value is determined depending upon the ratio of the first power.

7. The plasma processing apparatus according to claim 5 , wherein the second value is determined depending upon the ratio of the second power.

8. The plasma processing apparatus according to claim 5 , wherein the first value is either load impedance in a case where the first power is in the high output or load impedance in case where the first power is in the low output.

9. The plasma processing apparatus according to claim 5 , wherein the second value is either load impedance in a case where the second power is in the high output or load impedance in case where the second power is in the low output.

10. The plasma processing apparatus according to claim 5 , wherein the first value is determined depending upon the ratio of the first power and is either load impedance in a case where the first power is in the high output or load impedance in a case where the first power is in the low output.

11. The plasma processing apparatus according to claim 5 , wherein the second value is determined depending upon the ratio of the second power and is either load impedance in a case where the second power is in the high output or load impedance in a case where the second power is in the low output.

12. The plasma processing apparatus according to claim 4 wherein the second value is determined depending upon the ratio of the second power.

13. The plasma processing apparatus according to claim 4 , wherein the second value is either load impedance in a case where the second power is in the high output or load impedance in case where the second power is in the low output.

14. The plasma processing apparatus according to claim 4 , wherein the first value is determined depending upon the ratio of the second power and is either load impedance in a case where the first power is in the high output or load impedance in a case where the first power is in the low output.

15. The plasma processing apparatus according to claim 4 , wherein the second value is determined depending upon the ratio of the second power and is either load impedance in a case where the second power is in the high output or load impedance in a case where the second power is in the low output.

Assignees

• Hitachi High Tech Corp

Inventors

• Terauchi Hiromitsu
• Iida Tsutomu
• Yamamoto Koichi

Classifications

• H10P50/267 Primary

  using plasmas · CPC title

• H01J37/32183 Primary

  Matching circuits · CPC title

• H01J37/3299

  Feedback systems · CPC title

• H01J37/32174

  Circuits specially adapted for controlling the RF discharge · CPC title

• H01L21/32136 Primary

  Electricity · mapped topic