Large-area, laterally-grown epitaxial semiconductor layers

Patent metadata

Field	Value
Publication number	US-9711352-B2
Application number	US-201414776634-A
Country	US
Kind code	B2
Filing date	Mar 14, 2014
Priority date	Mar 15, 2013
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Structures and methods for confined lateral-guided growth of a large-area semiconductor layer on an insulating layer are described. The semiconductor layer may be formed by heteroepitaxial growth from a selective growth area in a vertically-confined, lateral-growth guiding structure. Lateral-growth guiding structures may be formed in arrays over a region of a substrate, so as to cover a majority of the substrate region with laterally-grown epitaxial semiconductor tiles. Quality regions of low-defect, stress-free GaN may be grown on silicon.

First claim

What is claimed is:

1. A method for covering an area of a substrate with a semiconductor, the method comprising:
forming a first insulating layer to cover a crystal seed structure, wherein the first insulating layer also covers the area of the substrate;
opening at least one opening in the first insulating layer to expose at least one selective growth area that exposes a surface area of the seed structure;
forming a second insulating layer parallel to the first insulating layer and spaced apart from the first insulating layer by a distance;
removing a sacrificial material between the second insulating layer and first insulating layer region to form a lateral-growth guiding region for at least one selective growth area;
heteroepitaxially growing the semiconductor under first growth conditions into the lateral-growth guiding region from the at least one selective growth area;
removing the second insulating layer;
epitaxially growing the semiconductor under second growth conditions to form at least one semiconductor tile covering a portion of the area of the substrate;
depositing the sacrificial material over the first insulating layer;
depositing the second insulating layer over the sacrificial material; and
etching vias through the sacrificial material to expose surface areas of the first insulating layer, wherein forming the second insulating layer comprises filling the vias in the sacrificial material with the second insulating material.

2. The method of claim 1 , wherein the distance is between approximately 0.2 μm and approximately 2 μm.

3. The method of claim 1 , wherein a lateral extent of the at least one opening in the first insulating layer is between approximately 0.2 μm and approximately 10 μm.

4. The method of claim 1 , wherein the semiconductor is GaN.

5. The method of claim 4 , further comprising growing the gallium nitride under the first growth conditions to a lateral extent between approximately 5 μm and approximately 50 μm from the at least one opening, and wherein the distance is between approximately 0.2 μm and approximately 2 μm.

6. The method of claim 4 , further comprising growing the gallium nitride tile to a thickness between approximately 0.2 μm and approximately 2 μm.

7. The method of claim 4 , wherein growing the GaN under the first growth conditions comprises forming a close-packed plane of the GaN parallel to a direction of the lateral growth.

8. The method of claim 4 , wherein both the first growth conditions and the second growth conditions comprise providing a first gas containing nitrogen and a second gas containing gallium to the selective growth area.

9. The method of claim 8 , wherein the first gas is ammonia and the second gas is trimethylgallium.

10. The method of claim 9 , wherein a temperature for the first growth conditions is between approximately 950° C. and approximately 1050° C.

11. The method of claim 9 , wherein a pressure for the first growth condition is between approximately 100 mbar and approximately 400 mbar.

12. The method of claim 9 , wherein a flow rate of the first gas for the first growth condition is between approximately 0.5 slm to approximately 3 slm.

13. The method of claim 9 , wherein a flow rate of the second gas for the first growth condition is between approximately 40 μmol per minute and approximately 110 μmol per minute.

14. The method of claim 9 , wherein a temperature during the second growth condition is between approximately 1050° C. and approximately 1100° C.

15. The method of claim 9 wherein a pressure during the second growth condition is between approximately 40 mbar and approximately 100 mbar.

16. The method of claim 9 , wherein a flow rate of the first gas for the second growth condition is between approximately 2 slm and approximately 5 slm.

17. The method of claim 9 , wherein a flow rate of the second gas for the second growth condition is between approximately 20 μmol per minute and approximately 40 μmol per minute.

18. The method of claim 8 , wherein the ratio of gallium to nitrogen for the second growth condition is higher than a ratio of gallium to nitrogen for the first growth condition.

19. The method of claim 8 , where in a pressure for the first growth condition is approximately equal to or higher than a pressure for the second growth condition.

20. The method of claim 8 , wherein a temperature for the second growth condition is approximately equal to or higher than a temperature for the first growth condition.

21. The method of claim 1 , wherein forming the first insulating layer comprises depositing a dielectric material to cover the crystal seed structure.

22. The method of claim 21 , wherein the dielectric material comprises silicon nitride or silicon oxide.

23. The method of claim 1 , wherein opening at least one opening in the first insulating layer comprises etching a via through the first insulating layer.

24. The method of claim 1 , wherein the seed structure comprises aluminum nitride.

25. The method of claim 1 , wherein the seed structure comprises a multilayer stack including at least one layer of gallium nitride.

26. The method of claim 1 , wherein the second insulating layer comprises an oxide or a nitride.

27. The method of claim 1 , wherein the sacrificial material comprises polysilicon.

28. The method of claim 1 , wherein the removing the sacrificial material comprises etching the sacrificial material with a wet or dry etching process.

29. The method of claim 28 , wherein the dry etching process comprises an etching process that uses the gas XeF.sub.2.

30. The method of claim 29 , wherein a pressure during the etching is between approximately 1 Torr and approximately 20 Torr.

31. The method of claim 29 , wherein a flow rate of the XeF.sub.2 is between approximately 0.5 slm and approximately 2 slm.

Assignees

• Univ Yale

Inventors

• Han Jung
• Song Jie
• Chen Danti

Classifications

• H10P14/3216

  Nitrides · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/2922

  being non-crystalline insulating materials, e.g. glass or polymers · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P14/276

  Lateral overgrowth · CPC title