Dynamic non-volatile memory operation scheduling for controlling power consumption of solid-state drives

Patent metadata

Field	Value
Publication number	US-9711232-B2
Application number	US-201514967220-A
Country	US
Kind code	B2
Filing date	Dec 11, 2015
Priority date	Sep 22, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A memory device and a method for rescheduling memory operations for dynamically controlling power consumption of the memory device is disclosed. The method includes receiving a plurality of memory operations for a plurality of memory arrays of a memory device via a memory channel; storing the plurality of memory operations in a plurality of queues associated with the memory array; receiving a power budget associated with the plurality of memory arrays; determining one or more candidate memory operations in the plurality of queues to meet the power budget for a time window; dynamically rearranging the plurality of memory operations in the plurality of queues and generating rescheduled memory operations that meet the power budget for the time window; and fetching the rescheduled memory operations to the plurality of memory arrays.

First claim

What is claimed is:

1. A method comprising:
receiving a plurality of memory operations for one or more memory arrays of a memory device via a memory channel;
storing the plurality of memory operations in one or more queues associated with the memory array;
receiving a variable power budget associated with the one or more memory arrays in a power limit command during a runtime;
determining that at least one memory operation causes the variable power budget to be exceeded within a first time window;
determining one or more candidate memory operations in the one or more queues that are scheduled to operate in a second time window after the first time window, wherein the one or more candidate memory operations have less power consumption than the at least one memory operation;
dynamically reordering the plurality of memory operations in the one or more queues and generating rescheduled memory operations by reordering the at least one memory operation out of the first time window and reordering the one or more candidate memory operations into the first time window; and
fetching the rescheduled memory operations to the one or more memory arrays.

2. The method of claim 1 , wherein a set of possible memory operations of the plurality of memory operations includes a read operation, a slow page programming operation, a fast page programming operation, and an erase operation.

3. The method of claim 1 , wherein the rescheduled memory operations include a delay of a memory operation for a duration of the delay.

4. The method of claim 3 , wherein the duration of the delay is determined by the variable power budget.

5. The method of claim 1 , wherein the rescheduled memory operations include rearrangement of two memory operations in the same queue.

6. The method of claim 1 further comprising:
receiving the power limit command associated with the variable power budget via the memory channel.

7. The method of claim 1 further comprising:
receiving power feedback information; and
dividing the variable power budget into a series of time windows.

8. The method of claim 7 , wherein the power feedback information is generated by a thermostat or a power meter of the memory device.

9. The method of claim 1 further comprising:
determining the one or more candidate memory operations within a predetermined window in the queues based on a priority of the one or more candidate memory operations.

10. The method of claim 9 further comprising:
grouping power consumption in each of the time windows based on types of the memory operations; and
determining a total power consumption for each of the time windows based on the power consumption of the plurality of memory arrays.

11. A memory device comprising:
one or more memory arrays;
a memory channel configured to receive a plurality of memory operations for the one or more memory arrays from a host computer;
one or more queues configured to store the memory operations; and
a scheduler configured to:
receive a variable power budget associated with the plurality of memory arrays in a power limit command from the host computer during a runtime;
determine that at least one memory operation causes the variable power budget to be exceeded within a first time window;
determine one or more candidate memory operations in the one or more queues that are scheduled to operate in a second time window after the first time window, wherein the one or more candidate memory operations have less power consumption than the at least one memory operation;
dynamically reorder the plurality of memory operations in the one or more queues and generate rescheduled memory operations by reordering the at least one memory operation out of the first time window and reordering the one or more candidate memory operations into the first time window; and
fetch the rescheduled memory operations to the plurality of memory arrays.

12. The memory device of claim 11 , wherein a set of possible memory operations of the plurality of memory operations includes a read operation, a slow page programming operation, a fast page programming operation, and an erase operation.

13. The memory device of claim 11 , wherein the rescheduled memory operations include a delay of a memory operation for a duration of the delay.

14. The memory device of claim 13 , wherein the duration of the delay is determined by the variable power budget.

15. The memory device of claim 11 , wherein the rescheduled memory operations include rearrangement of two memory operations in the same queue.

16. The memory device of claim 11 , wherein the scheduler is further configured to:
receive the power limit command associated with the variable power budget from the host computer via the memory channel.

17. The memory device of claim 11 , wherein the scheduler is further configured to:
receive power feedback information.

18. The memory device of claim 17 , wherein the power feedback information is generated by a thermostat or a power meter of the memory device.

19. The memory device of claim 11 , wherein the scheduler is further configured to:
determine the one or more candidate memory operations within a predetermined window in the one or more queues based on a priority of the one or more candidate memory operations.

20. The memory device of claim 11 , wherein the variable power budget is divided into a series of time windows, and wherein the scheduler is further configured to:
group power consumption in each of the time windows based on types of the memory operations; and
determine a total power consumption for each of the time windows based on the power consumption of the plurality of memory arrays.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Inseok Stephen
• Ahn Byoung Young
• Ki Yang Seok

Classifications

• G11C16/30 Primary

  Power supply circuits · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G06F1/329

  by task scheduling · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title