Asynchronous FIFO buffer with Johnson code write pointer

Patent metadata

Field	Value
Publication number	US-9710415-B2
Application number	US-201414531992-A
Country	US
Kind code	B2
Filing date	Nov 3, 2014
Priority date	Nov 3, 2014
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

An asynchronous data transfer system includes a bus interface unit (BIU), a FIFO write logic module, a write pointer synchronizer, a write pointer validator, a FIFO read logic module, and an asynchronous FIFO buffer. The FIFO buffer receives a variable size data from the BIU and stores the variable size data at a write address. The FIFO write logic module generates a write pointer by encoding the write address using a Johnson code. The FIFO read logic module receives a synchronized write pointer at the asynchronous clock domain and generates a read address signal when the synchronized write pointer is a valid Johnson code format. The FIFO buffer transfers the variable size data to a processor based on the read address signal.

First claim

The invention claimed is:

1. A system for transferring input data to an asynchronous clock domain, the system comprising:
a write address generator for receiving a write increment signal and a write clock signal, incrementing a write address count value, and generating a write address signal;
a write pointer encoder, connected to the write address generator, for receiving the write address count value, encoding the write address count value using a Johnson code, and generating a write pointer;
a write pointer synchronizer, connected to the write pointer encoder, for receiving a read clock signal and the write pointer, and outputting a synchronized write pointer;
a write pointer validator, connected to the write pointer synchronizer, for receiving the synchronized write pointer and generating a write pointer valid signal when the synchronized write pointer conforms to a Johnson code format;
a write pointer decoder, connected to the write pointer synchronizer and the write pointer validator, for receiving the synchronized write pointer and the write pointer valid signal, respectively, decoding the synchronized write pointer, and generating a synchronized write address count value;
a read address generator, connected to the write pointer decoder, for receiving a read increment signal, the read clock signal, and the synchronized write address count value, incrementing a read address count value based on the read increment signal and the synchronized write address count value, and generating a read address signal; and
an asynchronous first-in-first-out (FIFO) buffer, connected to the read and write address generators, for receiving the read and write address signals, respectively, storing the input data based on the write address signal, and transferring the input data to the asynchronous clock domain based on the read address signal.

2. The system of claim 1 , wherein the write pointer validator:
replicates the most significant bit (MSB) of the synchronized write pointer to generate a check code having a length equal to a length of the synchronized write pointer,
performs an XOR operation of the synchronized write pointer and the check code to generate a compare code,
generates a first count value of consecutive leading logic low bits of the compare code and a second count value of consecutive trailing logic high bits of the compare code,
sums the first and second count values to generate a third count value, and
generates the write pointer valid signal when the third count value is equal to a predetermined threshold.

3. The system of claim 1 , further comprising:
a bus interface unit, connected to a data bus for receiving the input data, and connected to the write address generator and the asynchronous FIFO buffer, for generating the write increment signal based on a length of the input data to be stored in the asynchronous FIFO buffer, and providing the input data to the asynchronous FIFO buffer and the write increment signal to the write address generator; and
a processor, connected to the asynchronous FIFO buffer and the read address generator, for generating the read increment signal based on a length of the input data to be read from the asynchronous FIFO buffer, providing the read increment signal to the read address generator, and receiving the input data from the asynchronous FIFO buffer based on the read increment signal.

4. The system of claim 1 , further comprising a read pointer encoder, connected to the read address generator, for receiving the read address count value, encoding the read address count value using the Johnson code, and generating a read pointer.

5. The system of claim 1 , further comprising:
a memory-empty calculator, connected to the write pointer decoder and the read pointer encoder, for receiving the synchronized write pointer and the read pointer, respectively, and generating a buffer empty signal when the synchronized write pointer equals the read pointer and when the synchronized write pointer and the read pointer conform to the Johnson code format, thereby indicating that the asynchronous FIFO buffer is empty.

6. The system of claim 5 , further comprising:
a read pointer synchronizer connected to the read pointer encoder, for receiving the write clock signal and the read pointer and outputting a synchronized read pointer; and
a read pointer validator, connected to the read pointer synchronizer, for receiving the synchronized read pointer, and generating a read pointer valid signal when the synchronized read pointer conforms to the Johnson code format.

7. The system of claim 6 , further comprising:
a read pointer decoder, connected to the read pointer synchronizer, for receiving the synchronized read pointer, connected to the read pointer validator for receiving the read pointer valid signal, and connected to the write address generator, for decoding the synchronized read pointer based on the read pointer valid signal, and providing a synchronized read address count value to the write address generator.

8. The system of claim 7 , wherein the write address generator further increments the write address count value based on the synchronized read address count value.

9. The system of claim 8 , further comprising a memory-full calculator, connected to the read pointer decoder and the write pointer encoder, for receiving the synchronized read pointer and the write pointer, respectively, generating an inverted synchronized read pointer, and generating a buffer full signal when the inverted synchronized read pointer equals the write pointer and when the synchronized read pointer and the write pointer conform to the Johnson code format, thereby indicating that the asynchronous FIFO buffer is full.

10. A system for transferring input data to an asynchronous clock domain, the system comprising:
a bus interface unit connected to a data bus for receiving the input data, and generating a write increment signal based on a length of the input data;
a first-in-first-out (FIFO) write logic module, connected to the bus interface unit, for receiving a write clock signal and the write increment signal, incrementing a write address count value, encoding the write address count value using a Johnson code, and generating a write pointer and a write address signal;
a write pointer synchronizer, connected to the FIFO write logic module, for receiving a read clock signal and the write pointer and outputting a synchronized write pointer;
a write pointer validator, connected to the write pointer synchronizer, for receiving the synchronized write pointer, and generating a write pointer valid signal when the synchronized write pointer conforms to a Johnson code format;
a FIFO read logic module for receiving the read clock signal and a read increment signal, and connected to the write pointer synchronizer and the write pointer validator for receiving the synchronized write pointer and the write pointer valid signal, respectively, decoding the synchronized write pointer, generating a synchronized write address count value, incrementing a read address count value based on the read increment signal and the synchronized write address count value, and generating a read address signal; and
an asynchronous first-in-first-out (FIFO) buffer connected to the FIFO write and FIFO read logic modules for receiving the write address and the read address signals, respectively, and to the bus interface unit for receiving the input data, for storing the input data based on the write address signal, and transferring the input data to the asynchronous clock domain based on the read address signal.

11. The system of claim 10 , wherein the write pointer validator further:
replicates the most sig

Assignees

• Singh Chanpreet
• Bajaj Kshitij
• Bhojak Abhineet Kumar
• Ladsaria Anisha
• Prasad Tejbal
• Nxp Usa Inc

Inventors

• Singh Chanpreet
• Bajaj Kshitij
• Bhojak Abhineet Kumar
• Ladsaria Anisha
• Prasad Tejbal

Classifications

• G06F13/1673

  using buffers · CPC title

• G06F2205/102

  Avoiding metastability, i.e. preventing hazards, e.g. by using Gray code counters · CPC title

• G06F13/4239 Primary

  with asynchronous protocol · CPC title

• G06F2205/067

  Bidirectional FIFO, i.e. system allowing data transfer in two directions · CPC title

• G06F5/14

  for overflow or underflow handling, e.g. full or empty flags · CPC title