Data transmission using PCIe protocol via USB port

Patent metadata

Field	Value
Publication number	US-9710406-B2
Application number	US-201414570304-A
Country	US
Kind code	B2
Filing date	Dec 15, 2014
Priority date	Dec 15, 2014
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Techniques for transmitted data through a USB port using a PCIe protocol are described herein. In one example, a method includes detecting a coupling of an apparatus and a PCIe compatible device via a Type-C connector and sending at least one vendor defined message to the PCIe compatible device. The method can also include receiving an alternate mode indicator corresponding to a data transfer via a PCIe protocol and sending an enter mode command to the PCIe compatible device to enable the data transfer between the apparatus and the PCIe compatible device via the PCIe protocol. Furthermore, the method can include transferring data between the apparatus and the PCIe compatible device via the Type-C connector with the PCIe protocol.

First claim

What is claimed is:

1. An apparatus comprising:
a multiplexor; and
logic to:
detect a coupling of the apparatus and a PCIe compatible device via a Type-C connector;
detect support for role reversal;
send at least one vendor defined message to the PCIe compatible device;
receive a vendor identification and an alternate mode indicator corresponding to a data transfer via a PCIe protocol;
send an enter mode command to the PCIe compatible device to enable the data transfer between the apparatus and the PCIe compatible device via the PCIe protocol; and
transfer data between the apparatus and the PCIe compatible device via the Type-C connector with the PCIe protocol.

2. The apparatus of claim 1 , wherein the logic is to send the alternate mode indicator to an application or hardware component of the apparatus to indicate that the apparatus is to transmit data to the PCIe compatible device using a PCIe protocol.

3. The apparatus of claim 1 , further comprising an xHCI Host controller, and wherein the logic is to control the multiplexor to transmit data via the PCIe protocol or a USB protocol.

4. The apparatus of claim 3 , wherein the alternate mode indicator indicates whether the PCIe compliant device is configured to transmit data using the PCIe protocol.

5. The apparatus of claim 1 , wherein the multiplexor includes sideband logic.

6. The apparatus of claim 1 , wherein the logic sends a PCIe configure command to the multiplexor.

7. The apparatus of claim 6 , wherein the logic is to send the PCIe configure command to the multiplexor in response to receiving a programmable instruction, in response to embedded logic, or in response to a runtime process.

8. The apparatus of claim 1 , wherein the logic comprises isolation circuitry to generate an error in response to detecting the data from the PCIe compliant device is transmitted using a protocol not supported by the logic.

9. A method for transmitting data via a USB port, the method comprising:
detecting a coupling of an apparatus and a PCIe compatible device via a Type-C connector;
detecting support for role reversal;
sending at least one vendor defined message to the PCIe compatible device;
receiving an alternate mode indicator corresponding to a data transfer via a PCIe protocol;
sending an enter mode command to the PCIe compatible device to enable the data transfer between the apparatus and the PCIe compatible device via the PCIe protocol; and
transferring data between the apparatus and the PCIe compatible device via the Type-C connector with the PCIe protocol.

10. The method of claim 9 , comprising sending the alternate mode indicator to an application or hardware component of the apparatus to indicate that the apparatus is to transmit data to the PCIe compatible device using a PCIe protocol.

11. The method of claim 10 , wherein the alternate mode indicator indicates whether the PCIe compliant device is configured to transmit data using the PCIe protocol.

12. The method of claim 9 , comprising controlling a multiplexor to transmit data via the PCIe protocol or a USB protocol.

13. The method of claim 12 , comprising sending a PCIe configure command to the multiplexor.

14. The method of claim 12 , comprising sending the PCIe configure command to the multiplexor in response to receiving a programmable instruction, in response to embedded logic, or in response to a runtime process.

15. The method of claim 9 , comprising generating an error in response to detecting the data from the PCIe compliant device is transmitted using a protocol not supported by the logic.

16. An apparatus for transmitting data comprising:
logic to:
detect a coupling of the apparatus and a serial expansion bus compatible device via a multi-mode connector;
detect support for role reversal;
send at least one vendor defined message to the serial expansion bus compatible device;
receive an alternate mode indicator corresponding to a data transfer via a serial expansion bus protocol;
send an enter mode command to the serial expansion bus compatible device to enable the data transfer between the apparatus and the serial expansion bus compatible device via the serial expansion bus protocol; and
transfer data between the apparatus and the serial expansion bus compatible device via the multi-mode connector with the serial expansion bus protocol.

17. The apparatus of claim 16 , comprising a multiplexor and sideband logic.

18. The apparatus of claim 17 , wherein the logic is to send a serial expansion bus configure command to the multiplexor in response to receiving a programmable instruction, in response to embedded logic, or in response to a runtime process.

19. The apparatus of claim 16 , wherein the logic comprises isolation circuitry to generate an error in response to detecting the data from the serial expansion bus compliant device is transmitted using a protocol not supported by the logic.

Assignees

• Intel Corp

Inventors

• Pethe Akshay G
• Harriman David J
• Wagh Mahesh
• Ismail Abdul Hawk

Classifications

• G06F13/4221 Primary

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/287

  Multiplexed DMA (G06F13/30 takes precedence) · CPC title

• G06F13/387

  for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system · CPC title