Systems and methods for flushing a cache with modified data

Patent metadata

Field	Value
Publication number	US-9710399-B2
Application number	US-201213561491-A
Country	US
Kind code	B2
Filing date	Jul 30, 2012
Priority date	Jul 30, 2012
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Systems and methods for flushing a cache with modified data are disclosed. Responsive to a request to flush data from a cache with modified data to a next level cache that does not include the cache with modified data, the cache with modified data is accessed using an index and a way and an address associated with the index and the way is secured. Using the address, the cache with modified data is accessed a second time and an entry that is associated with the address is retrieved from the cache with modified data. The entry is placed into a location of the next level cache.

First claim

We claim:

1. A method for flushing a cache with modified data, comprising:
responsive to a request to flush data from said cache with modified data to a next level cache, accessing said cache with modified data a first time using an index and a way and securing an address from said cache with modified data associated with said index and said way and providing said address to said next level cache, wherein said cache with modified data is a cache that maintains stores, wherein said cache with modified data is not included in said next level cache and wherein said request to flush data is a periodic request received to flush data from said cache with modified data;
using said address that is secured from said cache with modified data in response to said first time access, accessing said cache with modified data a second time and retrieving an entry that is associated with said address that is secured from said cache with modified data; and
placing said entry into a location of said next level cache.

2. The method of claim 1 wherein said request to flush data is automatically initiated periodically.

3. The method of claim 1 wherein said accessing said cache with modified data is facilitated by a probe that couples said cache with modified data and said next level cache.

4. The method of claim 3 , wherein said probe is controlled by said next level cache.

5. The method of claim 1 wherein said data is retrieved from said cache with modified data and placed into a location of said next level cache at the pipeline speed of said next level cache.

6. The method of claim 1 wherein said next level cache is a level two cache.

7. The method of claim 1 wherein said request to flush data from said cache is initiated to free up space for newer data based on an expectation that newer data will be received.

8. A cache system, comprising:
a level one cache comprising:
a store coalescing cache; and
a level two cache comprising:
a cache controller comprising:

a request accessing component for accessing a request to flush data from a cache with modified data to a next level cache, wherein said cache with modified data is a cache that includes stores, wherein said cache with modified data is not included in said next level cache and wherein said request to flush data is a periodic request received to flush data from said cache with modified data;
a cache accessing component for accessing said cache with modified data a first time using an index and a way and securing an address from said cache with modified data associated with said index and said way and providing said address to said next level cache;
accessing said cache with modified data a second time and retrieving an entry from said cache with modified data that is associated with said address, wherein said address is secured in response to said first time access; and
a writing component for placing said entry into a location of said next level cache.

9. The cache system of claim 8 wherein said request to flush data is automatically initiated periodically.

10. The cache system of claim 8 wherein said accessing said cache with modified data is facilitated by a probe that couples said cache with modified data and said next level cache.

11. The cache system of claim 8 wherein said data is retrieved from said cache with modified data and placed into a location of said next level cache at the pipeline speed of the next level cache.

12. The cache system of claim 8 wherein said next level cache is a level two cache.

13. A processor, comprising:
a CPU; and
a cache system, comprising:
a level one cache system comprising a store coalescing cache; and
a level two cache system comprising:
a cache controller comprising:
a request accessing component for accessing a request to flush data from a cache with modified data to a next level cache, wherein said cache with modified data is a cache that includes stores, wherein said cache with modified data is not included in said next level cache and wherein said request to flush data is a periodic request received to flush data from said cache with modified data;
a cache accessing component for accessing said cache a first time with modified data using an index and a way and securing an address from said cache with modified data associated with said index and said way and providing said address to said next level cache;
accessing said cache with modified data a second time and retrieving an entry from said cache with modified data that is associated with said address, wherein said address is secured in response to said first time access; and
a writing component for placing said entry into a location of said next level cache.

14. The processor of claim 13 wherein said request to flush data is automatically initiated periodically.

15. The processor of claim 13 wherein said accessing said cache with modified data is facilitated by a probe that couples said cache with modified data and said next level cache.

16. The processor of claim 13 wherein said data is retrieved from said cache with modified data and placed into a location of said next level cache at the pipeline speed of the next level cache.

Assignees

• Avudaiyappan Karthikeyan
• Abdallah Mohammad
• Intel Corp

Inventors

• Avudaiyappan Karthikeyan
• Abdallah Mohammad

Classifications

• G06F12/126 Primary

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title

• G06F12/0802

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F12/12

  Replacement control · CPC title

• G06F2212/70

  Details relating to dynamic memory management · CPC title