Dynamic address translation table allocation

Patent metadata

Field	Value
Publication number	US-9710395-B1
Application number	US-201615334588-A
Country	US
Kind code	B1
Filing date	Oct 26, 2016
Priority date	Oct 26, 2016
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A system and method dynamically allocate address translation tables for direct memory access windows by donating logical memory blocks to allocate to the address translation tables. A dynamic address translation table allocation module dynamically changes the allocation of memory to the address translation tables without a platform or partition reboot. A portion of the dynamic address translation table allocation module may reside in the hypervisor and in the partition and communicate to dynamically allocate memory to the address translation tables. The dynamic address translation table allocation module in the partition may donate logical memory blocks to the hypervisor to increase the allocation of memory to the address translation tables.

First claim

The invention claimed is:

1. An apparatus comprising:
at least one processor;
a memory coupled to the at least one processor;
an operating system residing in the memory and executed by the at least one processor;
a hypervisor residing in the memory and executed by the at least one processor that manages a plurality of logical partitions; and
a dynamic address translation table allocation module (DAAM) residing in the memory and executed by the at least one processor that dynamically changes the allocation of memory to the address translation tables using memory donated from the operating system, wherein the DAAM comprises an OS DAAM residing in the operating system and a hypervisor DAAM residing in the hypervisor.

2. The apparatus of claim 1 wherein the memory donated by the operating system is a logical memory block (LMB).

3. The apparatus of claim 1 wherein the OS DAAM queries the hypervisor for a maximum direct memory access (DMA) window size.

4. The apparatus of claim 3 wherein the OS DAAM determines the maximum DMA window size is not optimal and donates memory to the hypervisor to increase the address translation table size.

5. The apparatus of claim 4 wherein the OS DAAM donates memory by giving a logical memory block to the hypervisor.

6. The apparatus of claim 4 wherein a hypervisor DAAM in the hypervisor updates the size of the address translation table and calculates a new maximum DMA window size.

7. The apparatus of claim 6 wherein the OS DAAM creates a DMA window to maximize the input output performance of an adapter by sending a request to create a DMA window of the maximum size as determined by the hypervisor DAAM.

8. A computer-implemented method for dynamically changing direct memory access window size, the method comprising:
providing an operating system;
providing a hypervisor that manages a plurality of logical partitions;
dynamically changing size of a direct memory access (DMA) window by changing the allocation of memory to an address translation table using memory donated from the operating system to the hypervisor;
wherein the operating system queries the hypervisor for a maximum direct memory access (DMA) window size;
wherein the operating system determines the maximum DMA window size is not optimal and donates memory to the hypervisor to increase size of the address translation table; and
wherein the hypervisor updates the size of the address translation table and calculates a new maximum DMA window size.

9. The method of claim 8 wherein the memory donated by the operating system to the hypervisor is a logical memory block (LMB).

10. The method of claim 8 wherein the operating system creates an DMA window to maximize input output performance of an adapter by sending a request to create a DMA window of the maximum size as determined by the hypervisor.

11. The method of claim 10 wherein the hypervisor determines if the maximum DMA window size is optimal by determining if performance is acceptable with the maximum DMA window size, and where it is determined that performance is not acceptable determining if more memory is available to donate to the hypervisor.

12. A computer-implemented method for dynamically changing direct memory access window size, the method comprising:
providing an operating system on a processor;
providing a hypervisor that manages a plurality of logical partitions;
dynamically changing size of a direct memory access (DMA) window by changing allocation of memory to an address translation table using memory donated from the operating system to the hypervisor comprising:
the operating system querying the hypervisor for a maximum DMA window size, and if the maximum DMA window size is not optimal the operating system donates memory to the hypervisor to increase size of the address translation table;
the hypervisor updating the size of the address translation table and calculating a new maximum DMA window size;
the operating system creating a DMA window to maximize the input output performance of an adapter by sending a request to create a DMA window having the maximum DMA window size determined by the hypervisor; and

wherein the hypervisor determines if the maximum DMA window size is optimal by determining if performance is acceptable with the maximum DMA window size, and when it is determined that performance is not acceptable, determining if more memory in the operating system is available to donate to the hypervisor.

Assignees

• IBM

Inventors

• Garibay Vlctor A
• Hurlimann Daniel E
• Mehta Chetan
• Pizel Travis J
• Pizzano Fernando
• Sand Thomas R

Classifications

• G06F12/1081 Primary

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title

• G06F2212/65

  Details of virtual memory and virtual address translation · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title