Translation entry invalidation in a multithreaded data processing system

Patent metadata

Field	Value
Publication number	US-9710394-B2
Application number	US-201615083469-A
Country	US
Kind code	B2
Filing date	Mar 29, 2016
Priority date	Dec 22, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is removed and buffered in sidecar logic. While the translation invalidation request is buffered in the sidecar logic, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request. Subsequent memory referent instructions are ordered with respect to the broadcast synchronization request by a synchronization instruction.

First claim

What is claimed is:

1. A method of invalidating translation entries without deadlock in a multithreaded data processing system including a plurality of processor cores, the method comprising:
receiving, in a shared queue, storage-modifying requests of a plurality of concurrently executing hardware threads of an initiating processor core among the plurality of processor cores, wherein the plurality of storage-modifying requests includes a translation invalidation request of an initiating hardware thread among the plurality of hardware threads;
in response to receiving the translation invalidation request in the shared queue, removing the translation invalidation request from the shared queue and buffering the translation invalidation request in sidecar logic;
while the translation invalidation request is buffered in the sidecar logic, the sidecar logic broadcasting the translation invalidation request such that the translation invalidation request is received and processed by the plurality of processor cores;
in response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removing the translation invalidation request from the sidecar;
ensuring completion of processing of the translation invalidation request at all of the plurality of processor cores by a broadcast synchronization request; and
ordering subsequent memory referent instruction with reference to the broadcast synchronization request by execution of a synchronization instruction.

2. The method of claim 1 , and further comprising:
the initiating processor core pausing dispatch of instructions within the initiating hardware thread that follow the translation invalidation request in program order until an acknowledgment signal confirming completion of processing of the translation invalidation request at the initiating processor core is received.

3. The method of claim 1 , and further comprising:
in response to snooping broadcast of the translation invalidation request on a system fabric of the data processing system, a translation snoop machine remaining in an active state until a signal confirming completion of processing of the translation invalidation request at a snooping processor core affiliated with the translation snoop machine is received and thereafter returning to an inactive state.

4. The method of claim 1 , wherein:
the translation invalidation request specifies an effective address; and
in response to receiving the translation invalidation request at the initiating processing core:
the processor core invalidating one or more translation entries that translate the effective address;
the processor core waiting for one or more memory referent requests dependent on the one or more translation entries to drain from the initiating processor core; and
thereafter, the processor core transmitting a completion request to the shared queue providing confirmation of completion of processing of the translation invalidation request by the initiating processor core.

5. The method of claim 4 , and further comprising:
in response to the shared queue receiving the completion request, the shared queue ensuring that all older store requests within the shared queue have drained from the shared queue prior to removal of the translation invalidation request from the sidecar.

6. The method of claim 1 , wherein ensuring completion includes the sidecar logic broadcasting a translation synchronization request to all of the plurality of processor cores.

7. The method of claim 1 , and further comprising:
the initiating processor core generating the synchronization request by execution of a first synchronization instruction; and
the initiating processor core ordering execution of subsequent memory referent instructions with respect to the translation synchronization instruction through execution of a second synchronization instruction.

Assignees

• IBM

Inventors

• Guthrie Guy L
• Shen Hugh
• Williams Derek E

Classifications

• G06F12/084

  with a shared cache · CPC title

• G06F9/524

  Deadlock detection or avoidance · CPC title

• G06F12/0808

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• G06F2212/683

  Invalidation · CPC title

• G06F2212/1024

  Latency reduction · CPC title