Error correction based on historical bit error data

Patent metadata

Field	Value
Publication number	US-9710329-B2
Application number	US-201514871459-A
Country	US
Kind code	B2
Filing date	Sep 30, 2015
Priority date	Sep 30, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A data storage device includes a memory including a plurality of storage elements. The data storage device further includes a controller coupled to the memory. The controller includes an error correction code (ECC) engine. The controller further includes a reliability engine configured to access historical bit error data. The historical bit error data includes a first count of bit errors associated with a first set of storage elements of the plurality of storage elements. The reliability engine is configured to generate reliability information based on the historical bit error data and to provide the reliability information to the ECC engine.

First claim

What is claimed is:

1. A data storage device comprising:
a memory including a plurality of storage elements; and
a controller coupled to the memory, wherein the controller comprises:
an error correction code (ECC) engine; and
a reliability engine configured to access historical bit error data, wherein the historical bit error data includes a first count value of bit errors associated with a first group of storage elements of the plurality of storage elements, wherein the reliability engine is configured to generate reliability information based on the historical bit error data and to provide the reliability information to the ECC engine, and wherein the reliability engine is further configured to track, based data read from the first group of storage elements, a first number of errors having a first error type and a second number of errors having a second error type.

2. The data storage device of claim 1 , wherein the reliability engine is configured to access the historical bit error data from a controller memory and to update the historical bit error data based on the first number of errors and the second number of errors.

3. The data storage device of claim 1 , wherein the memory comprises a non-volatile memory, and wherein the reliability engine is configured to access the historical bit error data from the non-volatile memory.

4. The data storage device of claim 1 , wherein the reliability information indicates a reliability of a first plurality of bits read from the first group of storage elements, and wherein the ECC engine is configured to process the reliability information to decode the first plurality of bits read from the first group of storage elements.

5. The data storage device of claim 1 , wherein the historical bit error data includes a second count value of bit errors associated with a second group of storage elements of the plurality of storage elements, and wherein the first count value and the second count value of bit errors are determined based on decoding operations performed by the ECC during a lifetime of the memory.

6. The data storage device of claim 1 , wherein the reliability engine is further configured to to update the historical bit error data based on the first number of errors and the second number of errors.

7. The data storage device of claim 6 , wherein the reliability engine is further configured to send the updated historical bit error data to the memory.

8. The data storage device of claim 1 , wherein the ECC engine is configured to provide an indication of one or more bit errors to the reliability engine in response to detecting the one or more bit errors during a background scanning operation.

9. The data storage device of claim 1 , wherein the ECC engine is further configured to provide a no-error indicator to the reliability engine in response to no bit errors being detected during a decoding operation based on the data read from the first group of storage elements, and wherein the reliability engine is further configured to modify the first count value based on the no-error indicator.

10. The data storage device of claim 1 , wherein the ECC engine is further configured to determine one or more bit errors during a decoding process based on the data read from the first group of storage elements and to generate a timestamp associated with the one or more bit errors, and wherein a reliability information weight associated with the reliability information is based on the timestamp.

11. The data storage device of claim 1 , wherein the first error type is associated with a first reliability weight, and wherein the second error type is associated with a second reliability weight.

12. The data storage device of claim 1 , wherein the first group of storage elements includes multiple storage elements coupled to the same bit line.

13. A method comprising:
at a data storage device including a memory and a controller coupled to the memory,
wherein the memory includes a plurality of storage elements, performing:
accessing historical bit error data at the controller, wherein the historical bit error data includes a first count value of bit errors associated with a first group of storage elements of the plurality of storage elements;
generating reliability information based on the historical bit error data; and
tracking, based on data read from the first group of storage elements, a first number of errors having a first error type and a second number of errors having a second error type.

14. The method of claim 13 , wherein the reliability information indicates that the data read from the first group of storage elements has a first reliability level if the first count value exceeds a threshold.

15. The method of claim 14 , wherein the reliability information indicates that the data read from the first group of storage elements has a second reliability level if the first count value fails to exceed the threshold, and wherein the second reliability level is higher than the first reliability level.

16. The method of claim 13 , wherein the first error type corresponds to 0-to-1 errors, and wherein the second error type corresponds to 1-to-0 errors.

17. The method of claim 13 , wherein the first group of storage elements is coupled to a particular column of the memory, the particular column including multiple bit lines.

18. The method of claim 13 , wherein the first group of storage elements is coupled to a particular bit line of the memory.

19. The method of claim 13 , wherein the first group of storage elements comprises a first storage element coupled to a particular bit line and to a particular word line and a second storage element coupled to the particular bit line, wherein, if the first count value exceeds a threshold, the reliability information indicates that data read from a first subset of storage elements has the same reliability level as data read from the first storage element and that data read from a second subset of storage elements has a different reliability level than the data read from the first storage element.

20. An apparatus comprising:
means for generating reliability information based on historical bit error data, wherein the reliability information is associated with a first group of storage elements of a memory, wherein the historical bit error data includes a count value of bit errors associated with the first group of storage elements, wherein the count value indicates a number of times that data read from the first group of storage elements is detected as having an erroneous bit value during performance of decoding operations;
means for tracking, based on data read from the first group of storage elements, a first number of errors having a first error type and a second number of errors having a second error type; and
means for generating decoded data based on the reliability information and the data read from the first group of storage elements.

21. The apparatus of claim 20 , further comprising means for retrieving the historical bit error data from the memory in response to initiating a read operation at the memory.

22. The apparatus of claim 20 , further comprising means for updating the historical bit error data based on the first number of errors and the second number of errors.

23. The apparatus of claim 22 , wherein the updated historical bit error data is stored in the memory.

24. The method apparatus of claim 20 , further comprising means for updating the historical bit

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Golan Ronen
• Alrod Idan
• Elmoalem Eli

Classifications

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G06F11/1072 Primary

  in multilevel memories · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title