Dual in-line memory modules (DIMMs) supporting storage of a data indicator(s) in an error correcting code (ECC) storage unit dedicated to storing an ECC

Patent metadata

Field	Value
Publication number	US-9710324-B2
Application number	US-201514857491-A
Country	US
Kind code	B2
Filing date	Sep 17, 2015
Priority date	Feb 3, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A dual in-line memory module (DIMM) supporting storage of a data indicator(s) in an error correcting code (ECC) storage unit dedicated to storing an ECC. The DIMM is configured to provide a burst ECC storage unit striped in a burst data storage unit. The DIMM is configured to stripe a received burst data word across a burst data word storage unit at a write data address for a write operation. The DIMM is also configured to stripe a received burst ECC word for the burst data word across the burst ECC storage unit at the write data address in fewer bits than a number of data bit cells in the burst ECC storage unit. In this manner, the DIMM can store at least one data indicator for a burst data word in an extra, leftover bit(s) in the burst ECC storage unit.

First claim

What is claimed is:

1. A dual in-line memory module (DIMM), comprising:
a plurality of burst data storage units;
each burst data storage unit among the plurality of burst data storage units comprising:
a burst data word storage unit striped over a plurality of data line storage units totaling a burst length, each data line storage unit among the plurality of data line storage units comprising sixty-four (64) data bit cells; and
a burst error correcting code (ECC) storage unit striped over a plurality of ECC line storage units, each ECC line storage unit among the plurality of ECC line storage units corresponding to a data line storage unit, each ECC line storage unit comprising eight (8) data bit cells; and

the DIMM configured to:
receive a write data address for a burst memory write request;
receive burst write data of a burst write data block length for the burst memory write request, the burst write data comprising a burst write data word, a burst ECC word for the burst write data word, and at least one data indicator for the burst write data word;
stripe the received burst write data word across the burst data word storage unit at the received write data address;
stripe the received burst ECC word for the burst write data word across the burst ECC storage unit in fewer bits than a number of data bit cells in the burst ECC storage unit at the received write data address; and
store the at least one data indicator for the burst write data word in the burst ECC storage unit of the burst data storage unit at the received write data address.

2. The DIMM of claim 1 , wherein the at least one data indicator for the burst write data word is comprised of a single bit data indicator;
wherein the DIMM is configured to store the single bit data indicator for the burst write data word in a single bit of the burst ECC storage unit of the burst data storage unit at the received write data address.

3. The DIMM of claim 1 , wherein the at least one data indicator for the burst write data word is comprised of a multiple bit data indicator;
wherein the DIMM is configured to store the multiple bit data indicator for the burst write data word in multiple bits of the burst ECC storage unit of the burst data storage unit at the received write data address.

4. The DIMM of claim 1 , wherein the DIMM is configured to stripe the received burst ECC word for the burst write data word across the burst ECC storage unit in at least two fewer bits than the number of data bit cells in the burst ECC storage unit at the received write data address.

5. The DIMM of claim 1 , further configured to:
receive a memory read request comprising a read data address;
access the read data address to retrieve one or more burst read data stored at the read data address in the DIMM; and
communicate the one or more burst read data stored at the read data address to a memory controller, the one or more burst read data each comprising a burst read data word, a burst ECC word for the burst read data word, and the at least one data indicator for the burst read data word.

6. The DIMM of claim 1 , wherein the DIMM is configured to receive the at least one data indicator for the burst write data word indicating if the burst write data word is compressed.

7. The DIMM of claim 1 , wherein each burst data storage unit among the plurality of burst data storage units comprises the burst data word storage unit striped over four (4) data line storage units totaling the burst length.

8. The DIMM of claim 1 integrated into an integrated circuit (IC).

9. The DIMM of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; and a portable digital video player.

10. A method of writing data to a dual in-line memory module (DIMM) in a central processing unit (CPU)-based system, comprising:
receiving a memory write request in a DIMM, the memory write request comprising a write data address and burst write data of a burst write data block length, the burst write data comprising a burst write data word, a burst error correcting code (ECC) word for the burst write data word, and at least one data indicator for the burst write data word;
striping the received burst write data word across a burst data word storage unit in a burst data storage unit at the received write data address in the DIMM, the DIMM comprising:
a plurality of burst data storage units, each burst data storage unit among the plurality of burst data storage units comprising:
a burst data word storage unit striped over a plurality of data line storage units totaling a burst length, each data line storage unit among the plurality of data line storage units comprising sixty-four (64) data bit cells; and
a burst ECC storage unit striped over a plurality of ECC line storage units, each ECC line storage unit among the plurality of ECC line storage units corresponding to a data line storage unit, each ECC line storage unit comprising eight (8) data bit cells;

striping the received burst ECC word in the DIMM for the burst write data word across the burst ECC storage unit in fewer bits than a number of data bit cells in the burst ECC storage unit at the received write data address; and
storing the at least one data indicator for the burst write data word in the burst ECC storage unit of the burst data storage unit at the received write data address.

11. The method of claim 10 , wherein storing the at least one data indicator for the burst write data word in the burst ECC storage unit of the burst data storage unit at the received write data address comprises storing the at least one data indicator comprised of a single bit data indicator for the burst write data word in a single bit of the burst ECC storage unit of the burst data storage unit at the received write data address.

12. The method of claim 10 , wherein storing the at least one data indicator for the burst write data word in the burst ECC storage unit of the burst data storage unit at the received write data address comprises storing the at least one data indicator comprised of a multiple bit data indicator for the burst write data word in multiple bits of the burst ECC storage unit of the burst data storage unit at the received write data address.

13. The method of claim 10 , comprising striping the received burst ECC word for the burst write data word across the burst ECC storage unit in at least two fewer bits than the number of data bit cells in the burst ECC storage unit at the received write data address.

14. The method of claim 10 , further comprising:
receiving a memory read request comprising a read data address in the DIMM;
accessing the read data address in the DIMM to retrieve one or more burst read data stored at the read data address in the DIMM; and
communicating the one or more burst read data stored at the read data address to a memory controller, the one or more burst read data each comprising a burst read data word, a burst ECC word for the burst read data word, and the at least one data indicator for the burst read data word.

15. A memory system for a central processing unit (CPU)-based system, comprising:
a dual in-line memory mod

Assignees

• Qualcomm Inc

Inventors

• Trombley Michael Raymond

Classifications

• H03M13/17

  Burst error correction, e.g. error trapping, Fire codes · CPC title

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title