Replacing an accelerator firmware image without operating system reboot

Patent metadata

Field	Value
Publication number	US-9710254-B2
Application number	US-201514925768-A
Country	US
Kind code	B2
Filing date	Oct 28, 2015
Priority date	Oct 28, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

The present disclosure relates to updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator. According to one embodiment, while executing accelerator-enabled operations on the coherent hardware accelerator, a system stores a firmware update package in a local memory on the coherent hardware accelerator. Once the firmware update package is stored in local memory on the coherent hardware accelerator, the system restarting the coherent hardware accelerator by pausing the execution of at least a first operation initiated on the coherent hardware accelerator and applying the firmware update package to the firmware image on the coherent hardware accelerator. Once the firmware update package is applied to the coherent hardware accelerator, the system resumes the operation on the coherent hardware accelerator.

First claim

What is claimed is:

1. A computer program product comprising:
a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code configured to perform a function to update a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator, the function comprising:
while executing a set of operations on the coherent hardware accelerator, storing a firmware update package in a local memory on the coherent hardware accelerator;
restarting the coherent hardware accelerator by:
pausing the execution of at least a first operation initiated on the coherent hardware accelerator; and
applying the firmware update package to the firmware image on the coherent hardware accelerator; and

while resuming the paused operation on the coherent hardware accelerator, querying a configuration of the updated coherent hardware accelerator and making the configuration available to an operating system for discovery and use in one or more subsequent operations.

2. The computer program product of claim 1 , wherein pausing the first operation executing on the coherent hardware accelerator comprises saving at least one of:
one or more interrupt source numbers identifying the paused operation;
a range of memory mapped input/output (I/O) (MMIO) addresses associated with the paused operation;
a program counter associated with an instruction most recently executed by the paused operation; or
a most recently executed I/O command associated with the paused operation.

3. The computer program product of claim 2 , wherein resuming the paused operations comprises restoring at least one of the one or more interrupt source numbers, the range of MMIO addresses associated with the paused operation, the program counter associated with an instruction most recently executed by the operation, or the most recently executed I/O command associated with the operation.

4. The computer program product of claim 1 , wherein the function further comprises:
after pausing the first operation executing on the coherent hardware accelerator, resuming the paused operation using a software algorithm executing on a processor other than the hardware accelerator.

5. The computer program product of claim 1 , wherein the set of operations executing on the coherent hardware accelerator is paused in response to at least one of:
detecting a timeout condition when the set of operations attempts to transmit a command to the coherent hardware accelerator; or
detecting a reserved value when the set of operations queries the coherent hardware accelerator for a state of the coherent hardware accelerator.

6. The computer program product of claim 1 , wherein the first operation is included in the set, wherein the set of operations comprises a set of accelerator-enabled operations, wherein pausing the first operation executing on the coherent hardware accelerator comprises saving at least one of:
one or more interrupt source numbers identifying the paused operation;
a range of memory mapped input/output (I/O) (MMIO) addresses associated with the paused operation;
a program counter associated with an instruction most recently executed by the paused operation; or
a most recently executed I/O command associated with the paused operation.

7. The computer program product of claim 6 , wherein pausing the first operation executing on the coherent hardware accelerator comprises saving, in respective instances, each of:
the one or more interrupt source numbers identifying the paused operation;
the range of memory mapped input/output (I/O) (MMIO) addresses associated with the paused operation;
the program counter associated with the instruction most recently executed by the paused operation; and
the most recently executed I/O command associated with the paused operation.

8. The computer program product of claim 7 , wherein resuming the paused operation comprises restoring: at least one of the one or more interrupt source numbers, the range of MMIO addresses associated with the paused operation, the program counter associated with an instruction most recently executed by the operation, or the most recently executed I/O command associated with the operation.

9. The computer program product of claim 8 , wherein resuming the paused operation comprises restoring: at least one of the one or more interrupt source numbers, the range of MMIO addresses associated with the paused operation, the program counter associated with an instruction most recently executed by the operation, and the most recently executed I/O command associated with the operation.

10. The computer program product of claim 9 , wherein the function further comprises:
after pausing the operation executing on the coherent hardware accelerator, resuming the paused operation using a software algorithm executing on a processor other than the hardware accelerator.

11. The computer program product of claim 10 , wherein the set of operations executing on the coherent hardware accelerator is paused in response to at least one of:
detecting a timeout condition when the set of operations attempts to transmit a command to the coherent hardware accelerator; or
detecting a reserved value when the set of operations queries the coherent hardware accelerator for a state of the coherent hardware accelerator.

12. The computer program product of claim 11 , wherein the set of operations executing on the coherent hardware accelerator is paused in response to, in respective instances, each of:
detecting the timeout condition when the set of operations attempts to transmit the command to the coherent hardware accelerator; and
detecting the reserved value when the set of operations queries the coherent hardware accelerator for the state of the coherent hardware accelerator.

13. The computer program product of claim 12 , wherein the software algorithm executes on one or more computer processors executing the computer-readable program code, wherein the set of operations includes the one or more subsequent operations.

14. The computer program product of claim 1 , wherein the set of operations comprises a set of accelerator-enabled operations.

15. A system comprising:
a processor; and
a memory storing one or more instructions which, when executed by the processor, performs a function to update a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator, the function comprising:
while executing a set of operations on the coherent hardware accelerator, storing a firmware update package in a local memory on the coherent hardware accelerator;
restarting the coherent hardware accelerator by:
pausing the execution of at least a first operation initiated on the coherent hardware accelerator; and
applying the firmware update package to the firmware image on the coherent hardware accelerator; and

while resuming the paused operation on the coherent hardware accelerator, querying a configuration of the updated coherent hardware accelerator and making the configuration available to an operating system for discovery and use in one or more subsequent operations.

16. The system of claim 15 , wherein pausing the first operation executing on the coherent hardware accelerator comprises saving at least one of:
one or more interrupt source numbers identifying the paused operation;
a range of memory mapped input/output (I/O) (MMIO) addresses associated with the paused operation;
a program counter associated with an instruction most rec

Assignees

• IBM

Inventors

• Albot Andre L
• Aslot Vishal C
• Burks Iii Thomas V
• Dietel John D

Classifications

• G06F8/654

  using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories · CPC title

• G06F12/10

  Address translation · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F8/65 Primary

  Updates (security arrangements therefor G06F21/57) · CPC title