Apparatus and method for providing instruction for heterogeneous processor

Patent metadata

Field	Value
Publication number	US-9710241-B2
Application number	US-56409309-A
Country	US
Kind code	B2
Filing date	Sep 22, 2009
Priority date	Feb 18, 2009
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Provided are an apparatus and method for providing instructions for a heterogeneous processor having heterogeneous components supporting different data widths. Respective data widths of operands and connections in a data flow graph are determined by using type information of operands. Instructions, to be executed by the heterogeneous processor, are provided based on the determined data widths.

First claim

What is claimed is:

1. A compiling apparatus comprising:
an analysis unit configured to generate a data flow graph comprising nodes representing inputs, operations, and outputs, and connections representing data flows between the nodes, to determine data widths of input and output operands of the nodes and the connections in the data flow graph using type information regarding a type of the operands, and to add information about the determined data width of the input and output operands of the nodes and information about the connections between the nodes in the data flow graph; and
a data processing unit configured to provide instructions to be executed by a processor comprising heterogeneous components that support different data widths, based on the determined data widths of the operands and the connections in the data flow graph,
wherein the type information comprises a value indicating a number of bits, and the data processing unit is further configured to select, in response to respective determinations of the determined data widths of the operands and the connections in the data flow graph, instructions comprising a data width matching the determined data widths of the operands and the connections in the data flow graph, and
wherein the analysis unit is further configured to initialize data widths of input and output nodes in the data flow graph based on the type information of the operands and to determine and set, using a fixed-point algorithm, data widths of unknown operands and connections as minimal data widths thereof from among available data widths.

2. The compiling apparatus of claim 1 , wherein the heterogeneous components comprise at least one functional unit that processes data having a respective data width, register files that store data having different data widths, and connecting wires suitable for different data widths.

3. The compiling apparatus of claim 1 , wherein the data processing unit is further configured to determine functional units to execute the selected instructions.

4. The compiling apparatus of claim 1 , wherein the data processing unit is further configured to allocate registers based on the determined data widths of the operands and the connections in the data flow graph.

5. The compiling apparatus of claim 1 , wherein if the processor is a coarse grained array (CGA) processor, the data processing unit is further configured to determine data widths of input and output operands and connections of nodes existing on the CGA processor's routing paths, which are used for execution of the selected instructions, based on the determined data widths of the operands and the connections in the data flow graph.

6. The compiling apparatus of claim 5 , wherein the processor is a very long instruction word (VLIW) processor or a CGA processor.

7. A compiling method of a compiling apparatus, the compiling method comprising:
generating, by an analysis unit, a data flow graph comprising nodes representing inputs, operations, and outputs, and connections representing data flows between the nodes;
determining data widths of input and output operands of the nodes and the connections in the data flow graph using type information of the operands;
adding information about the determined data width of the input and output operands of the nodes and information about the connections between the nodes in the data flow graph; and
providing, by a data processing unit of the compiling apparatus, instructions to be executed by a heterogeneous processor comprising heterogeneous components that support different data widths, based on the determined data widths of the operands and the connections in the data flow graph,
wherein the type information comprises a value indicating a number of bits, and the providing of the instructions further comprises selecting, in response to respective determinations of the determined data widths of the operands and the connections in the data flow graph, instructions comprising a data width matching the determined data widths of the operands and the connections in the data flow graph, and
wherein the determining of the respective data widths of the operands and the connections in the data flow graph comprises:
initializing data widths of input and output nodes in the data flow graph based on the type information of the operands; and
determining and setting, using a fixed point algorithm, data widths of unknown operands and connections as minimal data widths thereof from among available data widths.

8. The compiling method of claim 7 , wherein the heterogeneous components comprise at least one functional unit that processes data having a respective data width, register files that store data having different data widths, and connecting wires suitable for different data widths.

9. The compiling method of claim 7 , wherein the providing of the instructions further comprises determining functional units to execute the selected instructions.

10. The compiling method of claim 7 , wherein the providing of the instructions further comprises allocating registers based on the determined data widths of the operands and the connections in the data flow graph.

11. The compiling method of claim 7 , wherein the providing of the instructions comprises, if the processor is a coarse grained array (CGA) processor, determining data widths of input and output operands and connections of nodes existing on the CGA processor's routing paths, which are used for execution of the selected instructions, based on the determined data widths of the operands and the connections in the data flow graph.

12. The compiling method of claim 7 , wherein the heterogeneous processor is a very long instruction word (VLIW) processor or a CGA processor.

13. A compiling apparatus comprising:
a processor configured to
generate a data flow graph comprising nodes representing inputs, operations, and outputs, and connections representing data flows between the nodes,
determine data widths of input and output operands of the nodes and the connections in the data flow graph using type information regarding a type of the operands, and
add, to the data flow graph, information about the determined data widths of the input and output operands of the nodes and information about the connections between the nodes in the data flow graph; and
provide instructions, to be executed by a processor comprising heterogeneous components that support different data widths, based on the determined data widths of the operands and the connections in the data flow graph,
select, in response to the determining of the data widths of the operands and the connections in the data flow graph, instructions comprising an operand data width corresponding to the determined data widths of the operands and the connections in the data flow graph, and
use initial data widths of operands and connections, determined using the type information, to determine unknown minimal data widths of operands and connections through an iterative process that repeats until the determined unknown data widths of operands and connections do not change.

14. The apparatus of claim 13 , further comprising a memory configured to store instructions,
wherein the processor is further configured to execute the instructions to configure the processor to:
generate a data flow graph comprising nodes representing inputs, operations, and outputs, and connections representing data flows between the nodes, to
determine data widths of input and output operands of the nodes and the connections in the data flow graph using type information regarding a type of the operands, and to
add, to the data flow grap

Assignees

• Bernhard Egger
• Ryu Soo-Jung
• Yoo Dong-Hoon
• Park Il-Hyun
• Samsung Electronics Co Ltd

Inventors

• Bernhard Egger
• Ryu Soo-Jung
• Yoo Dong-Hoon
• Park Il-Hyun

Classifications

• G06F9/3891

  organised in groups of units sharing resources, e.g. clusters · CPC title

• G06F8/41 Primary

  Compilation · CPC title

• G06F9/3012

  Organisation of register space, e.g. banked or distributed register file · CPC title