Enhanced capacitance touch screen display and methods for use therewith
US-2024411406-A1 · Dec 12, 2024 · US
US9710089B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9710089-B2 |
| Application number | US-201514894936-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 16, 2015 |
| Priority date | Jan 4, 2015 |
| Publication date | Jul 18, 2017 |
| Grant date | Jul 18, 2017 |
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A touch display panel, a manufacturing method thereof, a driving method and a touch display device are disclosed. The touch display panel comprises an array substrate and a color film substrate, wherein the array substrate comprises a first thin film transistor and a first detection line formed on a first substrate, and the color film substrate comprises a main spacer, an auxiliary spacer, a reference signal line and a second detection line formed on a second substrate. The bottom of the main spacer is connected to the reference signal line, the top of the main spacer is connected to a first source, the bottom of the auxiliary spacer is connected to the second detection line, and a projection of the top of the auxiliary spacer on the array substrate connects a first drain with the first detection line.
Opening claim text (preview).
What is claimed is: 1. A touch display panel comprising an array substrate and a color film substrate which is disposed in opposition to the array substrate; wherein the array substrate comprises a first thin film transistor and a first detection line formed on a first substrate, and the first thin film transistor comprises a first gate, a first active layer, a first source and a first drain; wherein the color film substrate comprises a main spacer, an auxiliary spacer, a reference signal line and a second detection line formed on a second substrate, both of the main spacer and the auxiliary spacer are conductors, and wherein the bottom of the main spacer is connected to the reference signal line, the top of the main spacer is connected to the first source, the bottom of the auxiliary spacer is connected to the second detection line, and a projection of the top of the auxiliary spacer on the array substrate connects the first drain with the first detection line. 2. The touch display panel according to claim 1 wherein the array substrate further comprises a gate line and a data line formed on the first substrate, wherein the gate line and the data line define a pixel unit in which a pixel electrode and a second thin film transistor are formed, and the second thin film transistor is connected to the gate line, the data line and the pixel electrode. 3. The touch display panel according to claim 2 wherein the second thin film transistor comprises a second gate, a second active layer, a second source and a second drain, wherein the second gate and the gate line are disposed at the same layer, wherein the second gate is formed on the first substrate, wherein a gate insulation layer is formed on the second gate, wherein the second active layer is formed on the gate insulation layer, wherein the second source and the second drain are formed at the same layer as the data line and are formed on the second active layer, wherein a passivation layer is formed on the second source and the second drain, wherein a via hole is formed in a region corresponding to the second drain in the passivation layer, and wherein the pixel electrode is connected to the second drain through the via hole; and wherein the first gate is the gate line, wherein the first active layer and the second active layer are disposed at the same layer, wherein an opening is formed in a region corresponding to the first active layer in the passivation layer, wherein the first source and the first drain are disposed at the same layer as the pixel electrode and are connected to the first active layer in the opening, and wherein the first detection line and the pixel electrode are disposed at the same layer. 4. The touch display panel according to claim 3 wherein a projection of the gate line on the color film substrate covers the reference signal line and the second detection line. 5. The touch display panel according to claim 3 wherein the reference signal line and the second detection line are disposed at the same layer, and the reference signal line and the second detection line are parallel to the gate line. 6. The touch display panel according to claim 3 wherein the first detection line is located right above the data line. 7. The touch display panel according to claim 1 wherein the color film substrate further comprises a color film layer and a black matrix formed on the second substrate, wherein a common electrode is formed on the black matrix, and the reference signal line and the second detection line are disposed at the same layer as the common electrode. 8. The touch display panel according to claim 1 wherein the main spacer comprises a main spacer body and a main spacer conductive layer disposed on outside surface of the main spacer body; wherein the auxiliary spacer comprises an auxiliary spacer body and an auxiliary spacer conductive layer disposed on outside surface of the auxiliary spacer body; and wherein the main spacer conductive layer and the reference signal line are integrally formed, and the auxiliary spacer conductive layer and the second detection line are integrally formed. 9. The touch display panel according to claim 1 wherein the height of the main spacer is greater than that of the auxiliary spacer. 10. A touch display device comprising a touch display panel according to claim 1 . 11. A method for manufacturing a touch display panel, wherein the touch display panel comprises an array substrate and a color film substrate disposed in opposition to the array substrate, and the method comprising: manufacturing the array substrate which comprises a first thin film transistor and a first detection line formed on a first substrate, the first thin film transistor comprising a first gate, a first active layer, a first source and a first drain; manufacturing the color film substrate which comprises a main spacer, an auxiliary spacer, a reference signal line and a second detection line formed on a second substrate, wherein both of the main spacer and the auxiliary spacer are conductors, wherein the bottom of the main spacer is connected to the reference signal line, the top of the main spacer is connected to the first source, and the bottom of the auxiliary spacer is connected to the second detection line; and aligning the array substrate with the color film substrate, such that the top of the main spacer is connected to the first source, and a projection of the top of the auxiliary spacer on the array substrate connects the first drain with the first detection line. 12. The method according to claim 11 wherein the array substrate further comprises a gate line and a data line formed on the first substrate, wherein the gate line and the data line define a pixel unit in which a pixel electrode and a second thin film transistor are formed, and wherein the second thin film transistor comprises a second gate, a second active layer, a second source and a second drain; and wherein the step of manufacturing the array substrate includes: forming the gate line and the second gate on the first substrate by means of a pattering process, the gate line being reused as the first gate of the first thin film transistor; forming a gate insulation layer on the gate lines and the second gate; forming the first active layer and the second active layer on the gate insulation layer by means of a pattering process; forming the data line, the second source and the second drain on the first active layer and the second active layer by means of a pattering process; forming a passivation layer on the data line, the second source and the second drain by means of a pattering process, such that a via hole is formed in a region corresponding to the second drain in the passivation layer, and an opening is formed in a region corresponding to the first active layer in the passivation layer; and forming the pixel electrode, the first source, the first drain and the first detection line on the passivation layer by means of a pattering process, wherein the pixel electrode is connected to the second drain through the via hole, and the first source and the first drain are connected to the first active layer in the opening. 13. The method according to claim 11 , wherein the color film substrate further comprises a color film layer and a black matrix formed on the second substrate, wherein a common electrode is formed on the black matrix, wherein the main spacer comprises a main spacer body and a main spacer conductive layer disposed on outside surface of the main spacer body, and wherein the auxiliary spacer comprises an auxiliary spacer body and an auxiliary spacer conductive layer disposed on outside surface of t
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