Timing optimized implementation of algorithm to reduce switching rate on high throughput wide buses

Patent metadata

Field	Value
Publication number	US-9710012-B2
Application number	US-201213684124-A
Country	US
Kind code	B2
Filing date	Nov 21, 2012
Priority date	Nov 21, 2012
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A dynamic bus inversion (DBI) circuit disposed between a transmitter and a receiver for generating an inversion control signal that is communicated to the receiver and used to perform inversion control on data communicated along a data path between the transmitter and the receiver includes a delay data setup circuit to receive the data from the transmitter. A majority vote function circuit is used to perform majority voting for consecutive bits of data output by the delay data setup circuit to generate majority data output. An inversion control circuit receives the majority data output, retrieves feedback data from a preceding inversion control output and interprets the two data to generate inversion control signal, which is used to perform inversion control on data along the data path before being communicated to the receiver. The inversion control signal is used by the receiver to interpret the data received from the data path.

First claim

What is claimed is:

1. A dynamic bus inversion (DBI) circuit, comprising:
delay data setup circuitry configured to produce consecutive bit outputs, each consecutive bit output corresponding to a distinct set of bits of consecutive data within a data path;
majority vote circuitry configured to generate majority data outputs by performing majority voting for the consecutive bit outputs, wherein the consecutive bit outputs are produced by the delay data setup circuitry prior to the consecutive data being transmitted on the bus of the data path; and
an inversion control circuit configured to generate inversion output signals used for performing inversion control on the bus, wherein, to generate the inversion output signal for data that is consecutive with preceding data in the data path, the inversion control circuit is configured to:
receive the majority data output from the majority vote circuitry,
retrieve feedback data, the feedback data comprising a preceding inversion output signal generated to perform inversion control for transmission of the preceding data on the bus, and
generate the inversion control signal for the data based on whether the preceding inversion signal corresponds to inversion of the preceding data for transmission on the bus, and whether the received majority data output for the data indicates that a majority of bits of the data differ from corresponding bits of the preceding data, the received majority data output generated from consecutive bit outputs produced prior to the preceding data being transmitted on the bus.

2. The circuit of claim 1 , wherein the data path comprises:
a data queue configured to store data to be transmitted on the bus of the data path; and
a selection circuit, the selection circuit receiving the inversion output signal generated by the inversion control circuit and selecting one of an inverted and non-inverted form of data obtained from the data queue for transmission on the bus based on the inversion output signal.

3. The circuit of claim 1 , wherein the delay data setup circuitry comprises a register configured to store the preceding data prior to the preceding data being transmitted on the bus and to produce the consecutive bit outputs in response to receiving the data, each consecutive bit output corresponding to a distinct set of bits, including a bit of the data and a corresponding bit of the preceding data stored in the register,
wherein the majority vote circuitry is configured to generate the majority data output by performing majority voting for the consecutive bit outputs.

4. The circuit of claim 1 , wherein the majority vote circuitry comprises a plurality of majority vote function circuits, each majority vote function circuit configured to perform majority voting for a respective one of the distinct sets of bits of consecutive data within the data path.

5. The circuit of claim 4 , wherein the delay data setup circuitry comprises a plurality of delay data setup circuits, each delay data setup circuit configured to produce a respective one of the consecutive bit outputs for a respective one of the majority vote function circuits.

6. The circuit of claim 5 , wherein each of the delay data setup circuits comprises a register to store a respective bit of the preceding data, and wherein each delay data setup circuit produces a respective consecutive bit output indicating whether one of the bits of the data differs from a corresponding bit of the preceding data.

7. The circuit of claim 5 , wherein a number of majority vote function circuits and a number of delay data setup circuits corresponds to a data bandwidth of the data path.

8. The circuit of claim 1 , wherein the inversion control circuit is configured to generate the inversion output signal for the data such that:
when the preceding inversion output signal corresponds to inversion of the preceding data on the bus, inversion control circuit generates the inversion output signal for the data to correspond to an inverse from the majority data output, and
when the preceding inversion output signal corresponds to non-inversion of the preceding data on the bus, the inversion control circuit generates the inversion output signal to correspond to the majority data output.

9. The circuit of claim 8 , wherein the inversion control circuit comprises logic configured to perform an XOR function on the received majority data output and the preceding inversion output signal.

10. The circuit of claim 1 , further comprising a transmitter configured to transmit the data with the inversion control signal generated for the data to a receiver on the bus, wherein the receiver comprises a DBI receive circuit configured to interpret the data transmitted on the bus using the transmitted inversion output signal.

11. A method for implementing dynamic bus inversion (DBI) on a bus of a data path, the method comprising:
generating a first inversion control signal, the first inversion control signal for performing inversion control for communication of the first data on the bus of the data path;
storing the first inversion control signal in a feedback register; and
generating a second inversion control signal, the second inversion control signal for performing inversion control for communication of second data on the bus, wherein the second data follows the first data consecutively in the data path, and wherein generating the second inversion control signal comprises:
storing data bits of the first data prior to performing the inversion control for communication of the first data on the bus,
forming a plurality of distinct sets of consecutive data bits, each of the distinct sets of consecutive data bits comprising a data bit of the second data and a stored data bit of the first data,
generating a majority data output for the second data using the distinct sets of consecutive data bits, wherein generating the majority data output for the second data comprises performing majority voting for each of the plurality of distinct sets of consecutive data bits,
retrieving the first inversion control signal from the feedback register, and
generating the second inversion control signal from the first inversion control signal and the majority data output, wherein the majority data output for the second data indicates whether a majority of the data bits of the second data differ from corresponding stored data bits of the first data, the corresponding data bits of the first data being stored prior to performing the inversion control for communication of the first data on the bus,

wherein the inverter uses the first inversion control signal to control inversion of the first data on the bus and uses the second inversion control signal to control inversion of the second data for communication on the bus.

12. The method of claim 11 , further comprising transmitting one or more of the first inversion control signal and the second inversion control signal on the bus.

13. The method of claim 11 , wherein the majority data output for the second data is generated by a majority vote function circuit that precedes an inversion control circuit in the data path.

14. The method of claim 11 , wherein generating the majority data output for the second data comprises performing majority voting for each of the plurality of distinct sets of consecutive data bits, each distinct set of consecutive data bits indicating whether corresponding data bits differ between the second data and the first data in parallel.

15. The method of claim 11 , wherein the majority voting is performed using a plurality of independent majority vote circuits, each majority vote

Assignees

• Sandisk Technologies Llc

Inventors

• Dalumi Efraim
• Lerner Eitan
• Cohen Baruch

Classifications

• G06F13/4234 Primary

  being a memory bus · CPC title

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic

• G06F1/14 Primary

  Time supervision arrangements, e.g. real time clock · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title