Printed wiring board, method for manufacturing the same and semiconductor device

Patent metadata

Field	Value
Publication number	US-9706663-B2
Application number	US-201514840693-A
Country	US
Kind code	B2
Filing date	Aug 31, 2015
Priority date	Sep 1, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A printed wiring board includes a first resin insulating layer, a first conductor pattern including first mounting pads formed on the first resin insulating layer, and a wiring structure positioned on the first resin insulating layer and including a second resin insulating layer and a second conductor pattern such that the second resin insulating layer and second conductor pattern are positioned adjacent to the first conductor pattern and that the second conductor pattern includes second mounting pads. The second mounting pads are embedded in the second resin insulating layer such that the second mounting pads have mounting surfaces exposed on an exposed surface of the second resin insulating layer, and the first mounting pads have mounting surfaces such that the mounting surfaces of the first and second mounting pads are formed on a same plane.

First claim

What is claimed is:

1. A printed wiring board, comprising:
a first resin insulating layer;
a first conductor pattern comprising a plurality of first mounting pads formed on the first resin insulating layer; and
a wiring structure positioned on the first resin insulating layer and comprising a second resin insulating layer and a second conductor pattern such that the second resin insulating layer and second conductor pattern are positioned adjacent to the first conductor pattern and that the second conductor pattern includes a plurality of second mounting pads,
wherein the plurality of second mounting pads is embedded in the second resin insulating layer such that the second mounting pads have mounting surfaces exposed on an exposed surface of the second resin insulating layer, and the first mounting pads have mounting surfaces such that the mounting surfaces of the first and second mounting pads are formed on a same plane.

2. The printed wiring board according to claim 1 , wherein the plurality of second mounting pads is embedded in the second resin insulating layer such that the mounting surfaces of the second mounting pads and the exposed surface of the second resin insulating layer are formed on the same plane.

3. The printed wiring board according to claim 1 , wherein the first conductor pattern and the second conductor pattern have surfaces formed on the same plane.

4. The printed wiring board according to claim 1 , wherein the mounting surfaces of the first and second mounting pads are roughened surfaces, respectively.

5. The printed wiring board according to claim 1 , wherein each of the mounting surfaces of the first and second mounting pads has a surface treatment film.

6. The printed wiring board according to claim 1 , wherein the plurality of second mounting pads is arrayed at intervals of 50 μm or less.

7. The printed wiring board according to claim 1 , wherein the wiring structure comprises a heat dissipation component.

8. The printed wiring board according to claim 7 , wherein the heat dissipation component of the wiring structure comprises one of a metal plate, a metal plating layer and a nano-carbon material.

9. The printed wiring board according to claim 1 , further comprising:
a bonding layer formed between the first resin insulating layer and the wiring structure such that the wiring structure is fixed to the first resin insulating layer.

10. The printed wiring board according to claim 1 , wherein the second resin insulating layer has a thermal expansion coefficient which is substantially equal to a thermal expansion coefficient of the first resin insulating layer.

11. The printed wiring board according to claim 1 , wherein the second conductor pattern comprises a wiring pattern having a line-space L/S which is smaller than a line-space L/S of a wiring pattern forming the first conductor pattern.

12. The printed wiring board according to claim 11 , wherein the wiring pattern of the second conductor pattern has the line-space L/S in a range of from 1 μm/1 μm to 5 μm/5 μm.

13. The printed wiring board according to claim 1 , wherein the plurality of second mounting pads is arrayed at intervals of 50 μm or less.

14. The printed wiring board according to claim 2 , wherein the wiring structure comprises a heat dissipation component.

15. The printed wiring board according to claim 2 , wherein the second resin insulating layer has a thermal expansion coefficient which is substantially equal to a thermal expansion coefficient of the first resin insulating layer.

16. The printed wiring board according to claim 2 , wherein the second conductor pattern comprises a wiring pattern having a line-space L/S which is smaller than a line-space L/S of a wiring pattern forming the first conductor pattern.

17. A semiconductor device, comprising:
the printed wiring board of claim 1 ; and
a plurality of electronic components mounted on the first and second mounting pads of the printed wiring board.

18. The semiconductor device according to claim 17 , wherein the printed wiring board is configured to electrically connect the electronic components mounted on the first and second mounting pads of the printed wiring board through the wiring structure.

Assignees

• Ibiden Co Ltd

Inventors

• Sakamoto Hajime
• Kunieda Masatoshi
• Terui Makoto
• Kariya Takashi

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/227

  Multiple bumps having different sizes · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title