Method and device for differential signal channel length compensation in electronic system

Patent metadata

Field	Value
Publication number	US-9706642-B2
Application number	US-86991010-A
Country	US
Kind code	B2
Filing date	Aug 27, 2010
Priority date	Aug 27, 2010
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

Embodiments of the present invention are directed to providing a time delay to a shortened trace in a differential microstrip trace pair. By adding back metal to a ground plane associated with a DC blocking capacitor, a time delay can be added to the shortened trace. The cutout associated with the longer trace remains unaltered. In a further embodiment, both cutouts can be modified with the addition of metal, with the cutout associated with the shorter trace receiving more metal than the other cutout. In a further embodiment of the present invention, a cutout associated with a connector can be modified to add back metal in the cutout. The cutout associated with the shorter trace is modified while the other cutout is left unchanged.

First claim

What is claimed is:

1. A substrate, comprising:
a first metal layer including a first trace and a second trace;
a second metal layer including a ground plane;
a dielectric layer arranged between the first and second metal layers;
a first solder pad and a second solder pad connected to the first trace and the second trace respectively; and
a first cutout and a second cutout in the ground plane corresponding with the first solder pad and the second solder pad respectively, wherein a length of the second trace is shorter than a length of the first trace, wherein an open area of the second cutout is less than an open area of the first cutout, wherein the ground plane is a single-layer ground plane, and wherein the second cutout includes a second perimeter that is substantially the same as a first perimeter of the first cutout, and the second cutout includes patterned metal interior to the second cutout.

2. The substrate of claim 1 , wherein the first metal layer further comprises a top layer of the substrate.

3. The substrate of claim 1 , wherein the second metal layer further comprises a bottom layer of the substrate.

4. The substrate of claim 1 , wherein the patterned metal interior of the second cutout comprises one or more metal members that extend across an inner space of the second cutout.

5. The substrate of claim 4 , wherein the one or more metal members includes at least one metal member that is perpendicular to another metal member.

6. The substrate of claim 1 , wherein the first trace, second trace, ground plane and dielectric layer form a differential microstrip transmission line.

7. The substrate of claim 1 , wherein the first solder pad and the second solder pad are associated with DC blocking capacitors.

8. The substrate of claim 1 , wherein the first solder pad and the second solder pad are associated with printed circuit board connectors.

9. The substrate of claim 1 , wherein the first solder pad and the second solder pad are vertically aligned with the first cutout and the second cutout respectively.

10. The substrate of claim 1 , wherein the first cutout is not contiguous with the second cutout.

11. A method of manufacturing a substrate, comprising:
providing a dielectric layer between a first metal layer and a second metal layer;
providing a ground plane on the second metal layer;
providing first and second traces on the first metal layer, wherein the first and second traces include first and second solder pads respectively, and wherein the second trace is shorter than the first trace; and
providing a first cutout and a second cutout in the ground plane, wherein the first and second cutouts correspond with the first and second solder pads respectively, an open area of the second cutout is smaller than an open area of the first cutout, wherein the ground plane is a single-layer ground plane, and wherein the providing the second cutout includes providing the second cutout with a second perimeter that is substantially the same as a first perimeter of the first cutout, and the second cutout includes patterned metal interior to the second cutout.

12. The method of claim 11 , wherein the first metal layer further comprises a top layer of the substrate.

13. The method of claim 11 , wherein the second metal layer further comprises a bottom layer of the substrate.

14. The method of claim 11 , wherein the providing the second cutout includes providing the patterned metal interior to the second cutout that comprises one or more metal members that extend across the open area of the second cutout.

15. The method of claim 14 , wherein the providing the second cutout includes providing one or more metal members that include at least one metal member that is perpendicular to another metal member.

16. The method of claim 11 , wherein the providing the dielectric layer, the first and second metal layers, the ground plane, and the first and second traces includes forming a differential microstrip transmission line.

17. The method of claim 11 , wherein the providing the first solder pad and the second solder pad is associated with a subsequent process of coupling DC blocking capacitors.

18. The method of claim 11 , wherein the providing the first solder pad and the second solder pad is associated with a subsequent process of coupling printed circuit board connectors.

19. The method of claim 11 , wherein the providing the first solder pad and the second solder pad includes vertically aligning the first solder pad and the second solder pad with the first cutout and the second cutout respectively.

20. A substrate, comprising:
a first metal layer including a first trace and a second trace;
a second metal layer including a ground plane;
a dielectric layer arranged between the first and second metal layers;
a first solder pad and a second solder pad connected to the first trace and the second trace respectively; and
a first cutout and a second cutout in the ground plane corresponding with the first solder pad and the second solder pad respectively, the first cutout and the second cutout having a first patterned metal interior and a second patterned metal interior respectively, wherein a length of the second trace is shorter than a length of the first trace, wherein the first patterned metal interior is different from the second patterned metal interior, and wherein the ground plane is a single-layer ground plane.

Assignees

• Lin Shengli
• Avago Technologies General Ip

Inventors

• Lin Shengli

Classifications

• H01P3/02

  with two longitudinal conductors · CPC title

• H05K1/0245

  Lay-out of balanced signal pairs, e.g. differential lines or twisted lines · CPC title

• H05K2201/10636

  Leadless chip, e.g. chip capacitor or resistor · CPC title

• H05K1/0225

  Single or multiple openings in a shielding, ground or power plane (H05K1/0227 takes precedence) · CPC title

• H05K1/0253 Primary

  Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings (H05K1/0251 takes precedence) · CPC title