High dynamic range and global shutter image sensor pixels having charge overflow signal detecting structures

Patent metadata

Field	Value
Publication number	US-9706142-B2
Application number	US-201514862859-A
Country	US
Kind code	B2
Filing date	Sep 23, 2015
Priority date	Sep 23, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a charge storage region, and a charge overflow circuit. The charge storage region may be used to operate the image sensor array in global shutter mode. During high light level illumination, the charge overflow circuit may divert charge away from the photodiode such that only a predetermined portion of the accumulated charge remains in the photodiode. During low light level illumination all of the accumulated charge may be stored in the pixel photodiode. The charge overflow circuit may include a transistor and a resistor or capacitor. By implementing a charge overflow circuit, the size of the charge storage region may be reduced while still preserving the high dynamic range and low noise of the image sensor during all light illumination conditions.

First claim

What is claimed is:

1. An image sensor pixel, comprising:
a photodiode that generates charge in response to image light;
a charge storage region that stores the generated charge;
a global shutter transistor coupled between the photodiode and the charge storage region, wherein the global shutter transistor is configured to transfer the generated charge from the photodiode to the charge storage region;
a capacitor;
a transistor coupled between the photodiode and the capacitor, wherein the transistor is configured to transfer overflow charge from the photodiode to the capacitor; and
a reset transistor, wherein the reset transistor is coupled between the capacitor and a gate terminal of the transistor and wherein the reset transistor is configured to reset a charge stored on the capacitor.

2. The image sensor pixel defined in claim 1 , wherein the transistor is configured to divert charge away from the photodiode and towards the capacitor when the generated charge reaches a given threshold level and wherein the transistor is configured to not divert any charge away from the photodiode when the generated charge is below the given threshold level.

3. The image sensor pixel defined in claim 1 , wherein the image sensor pixel is formed in a pixel substrate and wherein at least a portion of the charge storage region is formed in the pixel substrate directly below the global shutter transistor.

4. The image sensor pixel defined in claim 1 , wherein a source terminal of the reset transistor is coupled to a first terminal of the capacitor and wherein a second terminal of the capacitor is coupled to a drain terminal of the transistor.

5. The image sensor pixel defined in claim 4 , wherein the gate terminal of the transistor and a drain terminal of the reset transistor are each coupled to the second terminal of the capacitor.

6. The image sensor pixel defined in claim 5 , wherein the transistor includes predetermined channel potential adjustment implants.

7. The image sensor pixel defined in claim 5 , further comprising:
a floating diffusion node; and
an additional charge transfer transistor coupled between the floating diffusion node and the charge storage node, wherein the additional charge transfer transistor is configured to transfer the generated charge from the charge storage region to the floating diffusion node.

8. The image sensor pixel defined in claim 7 , further comprising:
a source follower transistor;
an addressing transistor; and
a pixel row address line, wherein the pixel row address line conveys row control signals to the addressing transistor to select the image sensor pixel to be read.

9. The image sensor pixel defined in claim 1 , wherein the charge storage region comprises a potential well and a threshold adjustment implant, wherein the potential well stores the generated charge and the threshold adjustment implant prevents generation of dark current.

10. The image sensor pixel defined in claim 1 , wherein the transistor comprises a junction gate transistor.

11. The image sensor pixel defined in claim 1 , wherein the transistor comprises a p-type doped barrier adjacent to an n+ type doped junction.

12. The image sensor pixel defined in claim 1 , further comprising:
an anti-blooming transistor that has a source terminal coupled to the photodiode.

13. The image sensor pixel defined in claim 1 wherein the charge storage region comprises a pinned diode.

14. An image sensor pixel, comprising:
a photodiode that generates charge in response to image light;
a charge storage region that stores the generated charge;
a global shutter transistor coupled between the photodiode and the charge storage region, wherein the global shutter transistor is configured to transfer the generated charge from the photodiode to the charge storage region;
a capacitor; and
a transistor coupled between the photodiode and the capacitor, wherein the transistor is configured to transfer overflow charge from the photodiode to the capacitor, wherein a drain terminal of the transistor is connected to a gate terminal of the transistor and to the capacitor.

15. A system, comprising:
a central processing unit;
memory;
input-output circuitry; and
an imaging device, wherein the imaging device comprises:
an array of image sensor pixels, and
a lens that focuses an image onto the array, wherein a given one of the image sensor pixels comprises:
a photodiode that generates charge in response to image light;
a charge storage region configured to store charge generated by the photodiode;
a first charge transfer transistor coupled between the photodiode and the charge storage region, wherein a global shutter signal activates the first charge transfer transistor to transfer the generated charge from the photodiode to the charge storage region;
a capacitor, wherein the capacitor is configured to divert overflow charge away from the photodiode, wherein the capacitor comprises one of a plurality of capacitors configured to divert overflow charge away from corresponding photodiodes in the array of image sensor pixels, wherein the array of image sensor pixels comprises a plurality of image sensor pixels each having a respective one of the plurality of capacitors, and wherein each of the plurality of capacitors has a different respective capacitance value;
a floating diffusion region; and
a second charge transfer transistor coupled between the charge storage region and the floating diffusion node, wherein the second charge transfer transistor is configured to transfer the generated charge from the charge storage region to the floating diffusion region.

16. The system defined in claim 15 , wherein the given image sensor pixel further comprises:
a charge overflow transistor coupled between the photodiode and the capacitor, wherein a source terminal of the charge overflow transistor is coupled to the photodiode and a drain terminal of the charge overflow transistor is coupled to a first terminal of the capacitor.

17. The system defined in claim 16 , wherein the given image sensor pixel further comprises:
a reset transistor, wherein the reset transistor is coupled between the capacitor and a gate terminal of the charge overflow transistor and wherein the reset transistor is configured to reset a charge stored on the capacitor.

18. The system defined in claim 16 wherein the charge overflow transistor is configured to divert the overflow charge towards the capacitor when the generated charge reaches a given threshold level and wherein the charge overflow transistor is configured to not divert any charge away from the photodiode when the generated charge is below the given threshold level.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Hynecek Jaroslav

Classifications

• H04N25/622

  by controlling anti-blooming drains · CPC title

• H04N25/778

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

• H04N25/771

  comprising storage means other than floating diffusion · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/59 Primary

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title