High data rate multilevel clock recovery system

Patent metadata

Field	Value
Publication number	US-9705717-B2
Application number	US-201615376348-A
Country	US
Kind code	B2
Filing date	Dec 12, 2016
Priority date	Dec 9, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

First claim

We claim:

1. A clock recovery system, comprising:
an ADC (analog-to-digital converter) circuit configured to sample an analog signal in response to sample a clock signal and generate a digital signal comprising sequence of digital data samples, wherein the analog signal comprises a stream of data symbols, wherein each data symbol comprises a plurality n of symbol components, including at least a first symbol component and a second symbol component, and wherein each digital data sample corresponds to one data symbol in the analog signal;
a FFE (feed forward equalizer) circuit configured to remove precursor ISI (intersymbol interference) from the digital data samples and at least partially remove postcursor ISI from the digital data samples, and output FFE equalized data samples;
a DFE (decision feedback equalizer) circuit configured to remove a first component of postcursor ISI from the FFE equalized data samples, and output DFE equalized data samples, wherein the first component of postcursor ISI of a given data sample arises from the first symbol component of a previous data sample; and
a DFFE (decision feedforward equalizer) circuit configured to remove a second component of postcursor ISI from the DFE equalized data samples, and generate DFFE equalized data samples, wherein the second component of postcursor ISI of a given data sample arises from the second symbol component of a previous data sample;
wherein the DFFE circuit is further configured to remove all but one of the n symbol components from each DFFE equalized data sample, and output an equalized 2-level digital signal comprising a sequence of equalized 2-level data samples; and
wherein the DFFE circuit comprises:
a DFFE summer circuit configured to add a current DFE equalized data sample to each of a plurality of combinations of postcursor correction values and second symbol component values to generate a plurality of summed output values;
a DFFE multiplexer circuit connected to outputs of the DFFE summer circuit; and
a second component decode circuit configured to (i) determine a sign of the second symbol component of the current DFE equalized data sample, (ii) determine a sign of the second symbol component of a previous DFE equalized data sample, and (iii) output a control signal that indicates the determined signs of the second symbol components of the current and previous DFE equalized samples;
wherein the control signal output from the second component decode circuit controls the DFFE multiplexer circuit to select one of the summed output values as a DFFE equalized data sample.

2. The clock recovery system of claim 1 , wherein the DFFE summer circuit comprises:
a first summer circuit configured to output a first summed value by adding values −LSB and −LSBH1 to the current DFE equalized data sample;
a second summer circuit configured to output a second summed value by adding values −LSB and +LSBH1 to the current DFE equalized data sample;
a third summer circuit configured to output a third summed value by adding values +LSB and −LSBH1 to the current DFE equalized data sample;
a fourth summer circuit configured to output a fourth summed valued by adding values +LSB and +LSBH1 to the current DFE equalized data sample;
wherein the LSBH1 value comprises a precomputed postcursor correction value and the LSB values comprises a precomputed second symbol component value.

3. The clock recovery system of claim 1 , wherein the analog signal comprises 4-level PAM (pulse amplitude modulation) signal, wherein each data symbol comprises a most-significant bit (MSB) as the first symbol component, and a least significant bit (LSB) as the second symbol component, and wherein the equalized 2-level digital signal output from the DFFE circuit comprises only the MSB components of the data samples.

4. The clock recovery system of claim 1 , wherein the DFE circuit comprises:
a first summer circuit configured to add a postcursor correction value to a current FFE equalized data sample;
a second summer circuit configured to subtract the postcursor correction value from the current FFE equalized data sample;
a multiplexer circuit connected to an output of each of the first and second summer circuits; and
first component decode circuit configured to determine a sign of the first symbol component of a previous FFE equalized data sample, and output a control signal that indicates the determined sign of the first symbol component of a previous FFE equalized data sample;
wherein the control signal output from the first component decode circuit controls the multiplexer circuit to select one of the outputs of the first and second summer circuit as a DFE equalized data sample.

5. The clock recovery system of claim 1 , further comprising control logic to precompute postcursor corrections values that are used by the DFE and DFFE circuits, and to precompute a component value for at least one of the symbol components that are removed from the DFFE equalized data samples.

6. The clock recovery system of claim 5 , wherein the control logic is configured to process an operating mode control signal to configure an operating mode of the clock recovery system for one of 2-level line modulation and 4-level line modulation.

7. The clock recovery system of claim 1 , further comprising control circuitry configured to process the equalized 2-level digital signal to determine an amount of any residual postcursor and precursor ISI of the equalized 2-level digital signal, and to adjust a phase of the sample clock signal that is applied to the ADC circuit to minimize the residual postcursor and precursor ISI of the equalized 2-level digital signal.

8. The clock recovery system of claim 7 , wherein the control circuitry comprises:
a sign error detection circuit configured to determine sign error values for the equalized 2-level data samples and sign values of the equalized 2-level data samples;
a phase detector circuit configured to process the sign error values and the sign values of the equalized 2-level data samples to determine early-late phase corrections signals;
a loop filter circuit configured to process the early-late phase correction signals and generate phase adjustment control signals; and
a phase adjustment circuit which receives the phase adjustment control signals from the loop filter circuit, and which is configured to adjust the phase of the sample clock signal that is applied to the ADC circuit to minimize the residual postcursor and precursor ISI of the equalized 2-level digital signal.

9. A digital receiver system, comprising:
an amplifier circuit configured to amplify a received analog signal, wherein the analog signal comprises a stream of data symbols, wherein each data symbol comprises a plurality (n) of symbol components, including at least a first symbol component and a second symbol component;
an ADC (analog-to-digital converter) circuit configured to sample the analog signal in response to a sample clock signal and generate a digital signal comprising sequence of digital data samples, wherein each digital data sample corresponds to one data symbol in the analog signal;
a digital equalization system configured to filter the digital signal to remove intersymbol interference and recover the stream of data symbols;
a clock recovery system configured to process the digital signal and generate the sample clock signal which is applied to the ADC circuit, wherein the clock recovery system comprises:
a FFE (feed forward equalizer) circuit configured to remove precursor ISI (intersymbol interference) from the digital data samples and at least partially remove postcursor ISI from the digital data samples, and output FFE equalized data samples;
a DFE (decision feedback equalizer)

Assignees

• IBM

Inventors

• Baecher Matthew B
• Beukema Troy J
• Msalka Lamiaa

Classifications

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04Q2213/03

  PAM · CPC title

• H04L43/028

  by filtering · CPC title

• H04L27/2275 Primary

  wherein the carrier recovery circuit uses the received modulated signals · CPC title

• H04L7/0334

  Processing of samples having at least three levels, e.g. soft decisions · CPC title