High speed low power digital to analog upconverter

Patent metadata

Field	Value
Publication number	US-9705522-B1
Application number	US-201615344328-A
Country	US
Kind code	B1
Filing date	Nov 4, 2016
Priority date	Nov 4, 2016
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

Systems and methods according to one or more embodiments are provided for a high speed digital to analog upconverter that provides for converting a plurality of parallel digital data bits to an analog output signal. In one example, a system includes a decoder circuit configured to receive a plurality of decoder input data bits and provide a plurality of decoded parallel digital data bits. The system also includes a mixer circuit configured to combine each of the decoded parallel digital data bits with a conversion clock signal to provide frequency shifted digital data bits, wherein the frequency shifted digital data bits are time misaligned with each other. The system also includes a synchronizer circuit configured to time align the frequency shifted digital data bits. The system further includes a switching network configured to generate an analog output signal in response to the time aligned frequency shifted digital data bits.

First claim

What is claimed is:

1. A system ( 100 ) comprising:
a decoder circuit ( 130 ) configured to receive a plurality of decoder input data bits ( 111 c ) and provide a plurality of decoded parallel digital data bits ( 111 d ), wherein the decoder circuit operates at a predefined sample rate (Fs);
a mixer circuit ( 140 ) coupled to the decoder circuit and configured to combine each of the decoded parallel digital data bits with a conversion clock signal ( 145 ) to provide frequency shifted digital data bits ( 111 e ), wherein the frequency shifted digital data bits are time misaligned with each other due to time misalignment associated with logic state transitions of each of the decoded parallel digital data bits and logic state transitions of the conversion clock signal;
a synchronizer circuit ( 105 ) coupled to the mixer circuit comprising a synchronizer clock signal ( 155 ) and configured to time align the frequency shifted digital data bits in response to the synchronizer clock signal; and
a switching network ( 102 ) coupled to the synchronizer circuit and configured to generate an analog output signal ( 106 ) in response to time aligned frequency shifted digital data bits ( 112 a ).

2. The system of claim 1 , wherein the mixer circuit is configured to translate the decoded parallel digital data bits at a first frequency (Fs) to the frequency shifted digital data bits at a second frequency (NFs), wherein the mixer circuit operates at a rate N times the predefined sample rate, and wherein the synchronizer circuit operates at a rate twice the mixer circuit rate.

3. The system of claim 1 , wherein the analog output signal comprises a bandwidth ( 1130 ) corresponding to a bandwidth of the decoder input data bits, and wherein a dominant spectral energy ( 1106 ) of the analog output signal is centered around a frequency (NFs) of the conversion clock signal.

4. The system of claim 1 , further comprising a multiplexer circuit ( 120 ) coupled to the decoder circuit and configured to receive a plurality of parallel digital data words ( 111 b ) in response to a multiplexer clock signal ( 125 ) and provide a corresponding one of the parallel digital data words ( 237 ) comprising the decoder input data bits at the predefined sample rate, wherein the multiplexer clock signal comprises a sample rate (Fs/M) 1/M times the predefined sample rate.

5. The system of claim 4 , further comprising a mesochronous interface “MCI” circuit ( 110 ) coupled to the multiplexer circuit and configured to receive a plurality of MCI input data words ( 111 a ) from an external source and synchronized by an external clock signal ( 115 ), and provide the plurality of parallel digital data words synchronized by the multiplexer clock signal, wherein the external clock signal is asynchronous to the multiplexer clock signal.

6. The system of claim 1 , wherein the mixer circuit is a first mixer circuit, the synchronizer circuit is a first synchronizer circuit, the switching network is a first switching network, and the analog output signal is a first analog output signal ( 106 a ), the system further comprising:
a second mixer circuit ( 140 b ) coupled to the decoder circuit and configured to combine each of the decoded parallel digital data bits with the conversion clock signal to provide frequency shifted digital data bits, wherein the frequency shifted digital data bits are time misaligned with each other;
a second synchronizer circuit ( 105 b ) coupled to the second mixer circuit comprising the synchronizer clock signal and configured to time align the frequency shifted digital data bits in response to the synchronizer clock signal;
a second switching network ( 102 b ) coupled to the second synchronizer circuit and configured to generate a second analog output signal ( 106 b ) in response to time aligned frequency shifted digital data bits wherein the second analog output signal is a complementary signal of the first analog output signal; and
wherein the decoder circuit, the first and second mixer circuit, the first and second synchronizer circuit, and the first and second switching network comprise single-ended complementary metal-oxide-semiconductor “CMOS” circuits ( 636 , 836 , 1036 ).

7. The system of claim 1 , wherein the synchronizer clock signal is a single ended clock signal, the system further comprising a dual-edge detector circuit ( 180 ) configured to convert a differential clock signal ( 175 ) having a first frequency (NFs) to the single ended clock signal having a second frequency (2NFs) that is twice the first frequency.

8. The system of claim 1 , wherein the switching network comprises a plurality of resistors ( 1023 , 1025 ) arranged in a parallel configuration, wherein corresponding ones of the resistors are coupled to corresponding ones of the time aligned frequency shifted digital data bits, and wherein the switching network further comprises a summing node ( 1008 ) coupled to the analog output signal, wherein each of the resistors are selectively coupled to the summing node in response to the corresponding time aligned frequency shifted data bit.

9. The system of claim 8 , wherein the switching network further comprises at least one bias resistor (R 39 ) coupled to the summing node at a first end and a voltage source (VDDA) at a second end, wherein the at least one bias resistor sets a bias voltage ( 1010 ) of the analog output signal, and wherein the at least one bias resistor and the resistors combine to fix an output impedance of the analog output signal.

10. A method comprising:
receiving ( 325 ), by a decoder circuit ( 130 ), a plurality of decoder input data bits ( 111 c );
providing ( 325 , 330 ), by the decoder circuit, a plurality of decoded parallel digital data bits ( 111 d ), wherein the decoder circuit operates at a predefined sample rate (Fs);
combining ( 335 ), by a mixer circuit ( 140 ) coupled to the decoder circuit, each of the decoded parallel digital data bits with a conversion clock signal ( 145 ) to provide frequency shifted digital data bits ( 111 e ), wherein the frequency shifted digital data bits are time misaligned with each other due to time misalignment associated with logic state transitions of each of the decoded parallel digital data bits and logic state transitions of the conversion clock signal;
aligning ( 340 ), by a synchronizer circuit ( 105 ) coupled to the mixer circuit, the frequency shifted digital data bits in response to a synchronizer clock signal ( 155 ); and
generating ( 345 ), by a switching network ( 102 ) coupled to the synchronizer circuit, an analog output signal ( 106 ) in response to time aligned frequency shifted digital data bits ( 112 a ).

11. The method of claim 10 , further comprising:
translating ( 335 ), by the mixer circuit, the decoded parallel digital data bits at a first frequency (Fs) to the frequency shifted digital data bits at a second frequency (NFs);
operating ( 335 ) the mixer circuit at a rate (NFs) N times the predefined sample rate; and
operating ( 340 ) the synchronizer circuit at a rate (2NFs) twice the mixer rate.

12. The method of claim 10 , wherein the analog output signal comprises a bandwidth ( 1130 ) corresponding to a bandwidth of the decoder input data bits, and wherein a dominant spectral energy ( 1106 ) of the analog output signal is centered around a frequency (NFs) of the conversion clock signal.

13. The method of claim 10 , further comprising:
receiving ( 320 ), by a multiplexer circuit ( 120 ) coupled to the decoder circuit, a plurality of parallel digital data words ( 111 b ) in response to a multiplexer clock signal ( 125 ); and
providing ( 320

Assignees

• Boeing Co

Inventors

• Ng Vincent T
• Ng Sharon S
• Wu Shihchang
• Martinez Pedro A
• Araki Nhung T

Classifications

• H03D7/125

  with field effect transistors · CPC title

• H03M1/10 Primary

  Calibration or testing · CPC title

• H03M1/66 Primary

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/662

  Multiplexed conversion systems · CPC title

• H03M1/808

  using resistors · CPC title