Circuit and method for generating reference signals for hybrid analog-to-digital convertors

Patent metadata

Field	Value
Publication number	US-9705520-B1
Application number	US-201615380246-A
Country	US
Kind code	B1
Filing date	Dec 15, 2016
Priority date	Sep 8, 2016
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.

First claim

What is claimed is:

1. A circuit, comprising:
a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC);
a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal; and
a second reference source coupled to an output of the filter, the second reference source configured to provide a second reference signal to the ADC, the second reference signal generated based on the filtered first reference signal.

2. The circuit of claim 1 , wherein the filter comprises a low-pass filter.

3. The circuit of claim 1 , wherein the first reference signal comprises a transient signal, and wherein a cutoff frequency of the filter is set based on a frequency of the transient signal.

4. The circuit of claim 3 , wherein the cutoff frequency of the filter is between about 5 times to about 10 times less than the frequency of the transient signal.

5. The circuit of claim 1 , further comprising the ADC.

6. The circuit of claim 5 , wherein the ADC comprises a hybrid ADC having a first stage and a second stage, and wherein the first stage and the second stage have differing ADC architectures.

7. The circuit of claim 6 , wherein the first stage of the hybrid ADC comprises a pipeline ADC, and the second stage of the hybrid ADC comprises at least one of a successive-approximation register (SAR) ADC, an asynchronous SAR ADC, a time-interleaved SAR ADC, or a time-interleaved asynchronous SAR ADC.

8. The circuit of claim 6 , wherein the first reference signal is provided to the first stage of the hybrid ADC, and the second reference signal is provided to the second stage of the hybrid ADC.

9. The circuit of claim 1 , wherein the first reference source comprises at least one of a fully differential amplifier or a plurality of single-ended voltage followers.

10. The circuit of claim 1 , wherein the second reference source comprises at least one of a fully differential amplifier or a plurality of single-ended voltage followers.

11. The circuit of claim 1 , wherein the second reference source comprises a first output terminal and a second output terminal, and wherein the circuit further comprises a capacitive element coupled between the first output terminal and the second output terminal of the second reference source.

12. A method, comprising:
generating a first reference signal for a first stage of a hybrid analog-to-digital convertor (ADC);
filtering the first reference signal to produce a filtered first reference signal; and
generating a second reference signal for a second stage of the hybrid ADC based on the filtered first reference signal.

13. The method of claim 12 , wherein filtering the first reference signal comprises low-pass filtering the first reference signal to produce the filtered first reference signal.

14. The method of claim 12 , wherein the first reference signal comprises a transient signal, and wherein the method further comprises:
determining a frequency of the transient signal of the first reference signal; and
determining a cutoff frequency of the filter based on the frequency of the transient signal.

15. The method of claim 12 , further comprising:
determining, using the first stage of the hybrid ADC and the first reference signal, first bits of a digital representation of an analog signal received at the first stage of the hybrid ADC; and
determining, using the second stage of the hybrid ADC and the second reference signal, second bits of the digital representation of the analog signal.

16. The method of claim 15 , wherein the digital representation is an N-bit digital representation of the analog signal, wherein the first bits comprise M most significant bits of the N-bit digital representation, and wherein the second bits comprise (N-M) least significant bits of the N-bit digital representation.

17. The method of claim 12 , wherein the first stage comprises a pipeline ADC, and the second stage of the hybrid ADC comprises at least one of a successive-approximation register (SAR) ADC, an asynchronous SAR ADC, a time-interleaved SAR ADC, or a time-interleaved asynchronous SAR ADC.

18. A circuit, comprising:
a hybrid analog-to-digital convertor (ADC) comprising a first ADC architecture coupled to a second ADC architecture different from the first ADC architecture, the first ADC architecture configured to receive an analog signal;
a first reference driver configured to provide a first reference signal to the first ADC architecture, the first reference signal for determining a first plurality of bits of a digital representation of the analog signal;
a low-pass filter coupled to an output of the first reference driver, the low-pass filter configured to filter the first reference signal to produce a filtered first reference signal; and
a second reference driver configured to generate a second reference signal based on the filtered first reference signal, and to provide the second reference signal to the second ADC architecture, the second reference signal for determining a second plurality of bits of the digital representation of the analog signal.

19. The circuit of claim 18 , further comprising a capacitive element coupled between a first output terminal and a second output terminal of the second reference driver.

20. The circuit of claim 18 , wherein the first reference signal comprises a first transient signal component generated by capacitor switching in the first ADC architecture, and wherein the low-pass filter is configured to remove the first transient signal component of the first reference signal.

21. The circuit of claim 20 , wherein a cutoff frequency of the low-pass filter is between about 5 times to about 10 times less than a frequency of the first transient signal component.

22. The circuit of claim 18 , wherein the first ADC architecture comprises a pipeline ADC architecture.

23. The circuit of claim 22 , wherein the pipeline ADC architecture is configured to determine a plurality of bit levels based on the first reference signal, the plurality of bit levels for determining the first plurality of bits of the digital representation of the analog signal.

24. The circuit of claim 18 , wherein the second ADC architecture comprises a successive-approximation register ADC architecture.

25. The circuit of claim 24 , wherein the successive-approximation register ADC architecture is configured to execute a search algorithm based on the second reference signal, the search algorithm for determining the second plurality of bits of the digital representation of the analog signal.

26. The circuit of claim 18 , further comprising at least one capacitive element coupled between an output terminal of the second reference driver and a supply voltage.

Assignees

• St Microelectronics Int Nv

Inventors

• Kumar Ashish
• Debnath Chandrajit
• Singh Pratap Narayan

Classifications

• H03M1/44

  Sequential comparisons in series-connected stages with change in value of analogue signal · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/1009

  Calibration · CPC title

• H03M1/0863 Primary

  of switching transients, e.g. glitches · CPC title

• H03M1/164

  the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence) · CPC title