Memory effect reduction using low impedance biasing

Patent metadata

Field	Value
Publication number	US-9705454-B2
Application number	US-201615207362-A
Country	US
Kind code	B2
Filing date	Jul 11, 2016
Priority date	Nov 4, 2013
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor.

First claim

What is claimed is:

1. A circuit comprising:
a bias circuit for a biased transistor, the bias circuit including a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to a gate of the biased transistor and configured to provide a bias voltage,
wherein the reference transistor has a first transconductance substantially identical to a second transconductance of the biased transistor,
wherein the gate of the biased transistor receives an additional input signal, and
wherein the master-slave source follower circuit comprises:
a master transistor configured to operate as a first source follower and provide a master reference voltage to the reference transistor; and
a slave transistor configured to operate as a second source follower and provide the bias voltage according to the master reference voltage.

2. The circuit of claim 1 , wherein a gate of the master transistor is coupled to a gate of the slave transistor.

3. The circuit of claim 1 , wherein the master transistor includes an NMOS transistor and wherein the slave transistor includes an NMOS transistor.

4. The circuit of claim 1 , further comprising:
a signal ground circuit coupled between the biased transistor and one or more components of the bias circuit,
wherein components of the bias circuit that are directly connected to the signal ground circuit do not generate significant return currents to a power supply ground.

5. The circuit of claim 4 , wherein all the components of the bias circuit that are directly connected to the signal ground circuit do not generate significant return currents to a power supply ground.

6. The circuit of claim 4 , wherein the signal ground circuit is directly connected to a power ground network at a location near the biased transistor.

7. The circuit of claim 6 , wherein the signal ground circuit is directly connected to a power ground network only at a location near the biased transistor.

8. The circuit of claim 1 , wherein the reference transistor is substantially identical to the biased transistor.

9. The circuit of claim 1 , further comprising:
a current source configured to generate a first current,
wherein the bias circuit is configured to generate a second current through the reference transistor that is substantially identical to the first current.

10. The circuit of claim 9 , wherein the current source is a programmable current source.

11. The circuit of claim 1 , wherein the circuit is provided in a single integrated circuit chip.

12. A circuit comprising:
a bias circuit for a biased transistor, the bias circuit including a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to a gate of the biased transistor and configured to provide a bias voltage; and
a coil having an end tap and a center tap,
wherein the reference transistor has a first transconductance substantially identical to a second transconductance of the biased transistor,
wherein the gate of the biased transistor receives an additional input signal,
wherein the end tap is coupled to the gate of the biased transistor, and
wherein the center tap is coupled to the bias circuit voltage output.

13. The circuit of claim 12 , wherein the coil is a coil of a transformer.

14. The circuit of claim 12 , further comprising:
a signal ground circuit coupled between the biased transistor and one or more components of the bias circuit,
wherein components of the bias circuit that are directly connected to the signal ground circuit do not generate significant return currents to a power supply ground.

15. The circuit of claim 12 , wherein the reference transistor is substantially identical to the biased transistor.

16. The circuit of claim 12 , further comprising:
a current source configured to generate a first current,
wherein the bias circuit is configured to generate a second current through the reference transistor that is substantially identical to the first current.

17. A method comprising:
generating a current in a reference transistor according to a first voltage generated using a master source follower circuit of a bias circuit;
generating a second voltage substantially identical to the first voltage using a slave source follower circuit of the bias circuit;
providing the second voltage to a gate of a biased transistor; and
providing an additional input voltage to the gate of the biased transistor,
wherein the reference transistor has a first transconductance substantially identical to a second transconductance of the biased transistor, and
wherein providing the second voltage to the biased transistor comprises:
providing the second voltage to a center tap of a coil,
wherein the biased transistor is coupled to an end tap of the coil.

18. The method of claim 17 , wherein the reference transistor is substantially identical to the biased transistor.

19. The method of claim 17 , further comprising:
providing a signal ground reference to one or more components of the bias circuit using a signal ground circuit,
wherein the ground circuit is connected to a power ground network at a location near the biased transistor, and
wherein components of the bias circuit that are directly connected to the signal ground circuit do not generate significant return currents to the power supply ground.

20. The method of claim 17 , wherein the coil is a coil of a transformer.

Assignees

• Marvell World Trade Ltd

Inventors

• Signoff David M
• He Ming
• Loeb Wayne A

Classifications

• H03F2200/555

  A voltage generating circuit being realised for biasing different circuit elements · CPC title

• H03F3/245 Primary

  with semiconductor devices only · CPC title

• G05F1/46

  wherein the variable actually regulated by the final control device is DC (G05F1/625 takes precedence) · CPC title

• H03F2200/453

  Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit · CPC title

• H03F3/265

  with field-effect transistors only · CPC title