Spin torque MRAM fabrication using negative tone lithography and ion beam etching

US9705077B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9705077-B2
Application numberUS-201514840176-A
CountryUS
Kind codeB2
Filing dateAug 31, 2015
Priority dateAug 31, 2015
Publication dateJul 11, 2017
Grant dateJul 11, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for forming a memory device includes masking a photoresist material using a reticle and a developer having a polarity opposite that of the photoresist to provide an island of photoresist material. A planarizing layer is etched to establish a pillar of planarizing material defined by the island of photoresist material. A metal layer is etched to form a metal pillar having a diameter about the same as the pillar of planarizing material. A memory stack is etched to form a memory stack pillar having a diameter about the same as the metal pillar. A magnetoresistive memory cell includes a magnetic tunnel junction pillar having a circular cross section. The pillar has a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer. A first conductive contact is disposed above the magnetic tunnel junction pillar. A second conductive contact is disposed below the magnetic tunnel junction pillar.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for forming a memory device, comprising: masking a photoresist material using a reticle and a developer having a polarity opposite that of the photoresist to provide an island of photoresist material; etching a planarizing layer with a first etch to establish a pillar of planarizing material defined by the island of photoresist material; etching a metal layer with a second etch to form a metal pillar having a diameter about the same as the pillar of planarizing material; and etching a memory stack with a third etch to form a memory stack pillar having a diameter about the same as the metal pillar. 2. The method of claim 1 , wherein the photoresist material is a positive tone photoresist material, the developer is a negative tone developer, and the reticle is a dark field reticle. 3. The method of claim 1 , wherein the photoresist material is a negative tone photoresist material, the developer is a positive tone developer, and the reticle is a bright field reticle. 4. The method of claim 3 , wherein the developer is n-butyl acetate. 5. The method of claim 1 , wherein the memory stack comprises a magnetic tunnel junction formed from a fixed layer, a tunnel barrier, and a free layer. 6. The method of claim 1 , wherein the island of photoresist material is circular. 7. The method of claim 1 , further comprising etching the pillar of planarizing material to reduce a diameter of the pillar of planarizing material before etching the metal layer. 8. The method of claim 7 , wherein etching the pillar of planarizing material reduces the diameter of the pillar of planarizing material to about 70 nm. 9. The method of claim 1 , further comprising etching the memory stack pillar to reduce a diameter of the memory stack pillar. 10. The method of claim 1 , wherein the island has a diameter of about 150 nm. 11. A method for forming a memory device, comprising: masking a photoresist material using a reticle and a developer having a polarity opposite that of the photoresist to provide an island of photoresist material; etching a planarizing layer with a first etch to establish a pillar of planarizing material defined by the island of photoresist material; etching the pillar with a second etch to reduce a diameter of the pillar of planarizing material; etching a metal layer with a third etch to form a metal pillar having a diameter about the same as the pillar of planarizing material; etching a memory stack with a fourth etch to form a memory stack pillar having a diameter about the same as the metal pillar; and etching the memory stack pillar with a fifth etch to reduce a diameter of the memory stack pillar. 12. The method of claim 11 , wherein the photoresist material is a positive tone photoresist material, the developer is a negative tone developer, and the reticle is a dark field reticle. 13. The method of claim 11 , wherein the photoresist material is a negative tone photoresist material, the developer is a positive tone developer, and the reticle is a bright field reticle. 14. The method of claim 11 , wherein the developer is n-butyl acetate. 15. The method of claim 11 , wherein the memory stack comprises a magnetic tunnel junction formed from a fixed layer, a tunnel barrier, and a free layer. 16. The method of claim 11 , wherein the island of photoresist material is circular.

Assignees

Inventors

Classifications

  • Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning · CPC title

  • details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

  • Multilevel magnetic memory cell using non-magnetic non-conducting interlayer, e.g. MTJ · CPC title

  • Resolution enhancement techniques not otherwise provided for, e.g. darkfield imaging, interfering beams, spatial frequency multiplication, nearfield lenses or solid immersion lenses · CPC title

  • Electricity · mapped topic

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What does patent US9705077B2 cover?
A method for forming a memory device includes masking a photoresist material using a reticle and a developer having a polarity opposite that of the photoresist to provide an island of photoresist material. A planarizing layer is etched to establish a pillar of planarizing material defined by the island of photoresist material. A metal layer is etched to form a metal pillar having a diameter abo…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H01L43/12. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 11 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).