Array substrate and manufacturing method thereof
US-12185597-B2 · Dec 31, 2024 · US
US9705008B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9705008-B2 |
| Application number | US-201414426152-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 19, 2014 |
| Priority date | Sep 2, 2014 |
| Publication date | Jul 11, 2017 |
| Grant date | Jul 11, 2017 |
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The present invention provides a manufacturing method and a structure of an oxide semiconductor TFT substrate, in which an oxide conductor layer is used to define a channel of an oxide semiconductor TFT substrate. Since the oxide conductor layer is relatively thin and compared to the known techniques, the width of the channel can be made smaller and the width of the channel can be controlled precisely, the difficult of the manufacturing process of the oxide semiconductor TFT substrate can be reduced and the performance of the oxide semiconductor TFT substrate can be enhanced and the yield rate of manufacture can be increased. In a structure of an oxide semiconductor TFT substrate manufactured with the present invention, since the oxide conductor layer and the oxide semiconductor layer are similar in structural composition, excellent ohmic contact can be formed; the oxide conductor does not cause metal ion contamination in the oxide semiconductor layer; and the oxide conductor layer is transparent so as to help increase aperture ratio.
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What is claimed is: 1. A manufacturing method of an oxide semiconductor thin-film transistor (TFT) substrate, comprising the following steps: Step 1: providing a substrate and depositing and patternizing an oxide conductor layer on the substrate to form an oxide conductor layer having a channel; Step 2: depositing and patternizing an oxide semiconductor layer on the oxide conductor layer to form an oxide semiconductor layer; Step 3: depositing a first insulation layer on the oxide semiconductor layer; Step 4: depositing and patternizing a first metal layer on the first insulation layer to form a gate terminal; Step 5: depositing a second insulation layer on the gate terminal; Step 6: subjecting the first insulation layer and the second insulation layer simultaneously to a patternization operation to form vias; and Step 7: forming a source terminal and a drain terminal on the second insulation layer. 2. The manufacturing method of an oxide semiconductor TFT substrate as claimed in claim 1 , wherein an operation of Step 7 comprises: depositing and patternizing a second metal layer on the second insulation layer, where the second metal layer fills up the vias and is electrically connected to the oxide semiconductor layer to form the drain terminal and the source terminal. 3. The manufacturing method of an oxide semiconductor TFT substrate as claimed in claim 1 , wherein an operation of Step 7 comprises: Step 71 : depositing and patternizing a second metal layer on the second insulation layer, where the second metal layer fills up the via and is electrically connected to the oxide semiconductor layer to form the drain terminal; and Step 72 : depositing and patternizing a second oxide conductor layer on the second insulation layer, where the second oxide conductor layer fills up the via and is electrically connected to the oxide semiconductor layer to form the source terminal. 4. The manufacturing method of an oxide semiconductor TFT substrate as claimed in claim 1 , wherein the substrate is a glass substrate and the patternizing operation is achieved with yellow light and etching processes. 5. The manufacturing method of an oxide semiconductor TFT substrate as claimed in claim 1 , wherein the oxide conductor layer is indium tin oxide (ITO) or indium zinc oxide (IZO) and the oxide conductor layer has a thickness less than a thickness of the drain terminal. 6. The manufacturing method of an oxide semiconductor TFT substrate as claimed in claim 3 , wherein the source terminal is ITO or IZO. 7. The manufacturing method of an oxide semiconductor TFT substrate as claimed in claim 1 , wherein the source terminal also functions as a pixel electrode and the oxide semiconductor layer is indium gallium zinc oxide (IGZO).
by chemical means · CPC title
Manufacture or treatment · CPC title
characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title
Electricity · mapped topic
Electricity · mapped topic
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