Semiconductor device

Patent metadata

Field	Value
Publication number	US-9705005-B2
Application number	US-201514828669-A
Country	US
Kind code	B2
Filing date	Aug 18, 2015
Priority date	Nov 20, 2009
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a substrate;
first to fourth insulating layers stacked in this order over the substrate; and
a first transistor, the first transistor comprising:
a first channel formation region including an oxide semiconductor layer between the second and the third insulating layers;
a first conductive layer over the third insulating layer and overlapping with the first channel formation region; and
third and fourth conductive layers on and in direct contact with the oxide semiconductor layer and below the third insulating layer;

wherein the first and the fourth insulating layers each comprise aluminum and oxygen; and
wherein the second and the third insulating layers each comprise oxygen.

2. The semiconductor device according to claim 1 ,
wherein the second and the third insulating layers are in direct contact with the oxide semiconductor layer.

3. The semiconductor device according to claim 1 ,
wherein the fourth insulating layer is in direct contact with the first conductive layer.

4. The semiconductor device according to claim 1 ,
wherein the fourth insulating layer is on and in direct contact with a top surface of the first conductive layer.

5. The semiconductor device according to claim 1 ,
wherein the substrate is a semiconductor substrate.

6. The semiconductor device according to claim 1 ,
wherein there is direct contact between at least the first and the second insulating layers, between the second and the third insulating layers, or between the third and the fourth insulating layers.

7. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer is formed from an In—Ga—Zn—O-based oxide semiconductor material.

8. A memory element comprising the semiconductor device according to claim 1 .

9. An electronic appliance comprising the semiconductor device according to claim 1 .

10. A semiconductor device comprising:
a substrate;
a second transistor comprising:
a second channel formation region including a non-oxide semiconductor layer;
a second conductive layer overlapping with the second channel formation region; and
a fifth insulating layer between the non-oxide semiconductor layer and the second conductive layer;

first to fourth insulating layers stacked in this order over the second channel formation region and over the second conductive layer; and
a first transistor, the first transistor comprising:
a first channel formation region including an oxide semiconductor layer between the second and the third insulating layers;
a first conductive layer over the third insulating layer and overlapping with the first channel formation region; and
third and fourth conductive layers on and in direct contact with the oxide semiconductor layer and below the third insulating layer;

wherein the first and the fourth insulating layers each comprise aluminum and oxygen; and
wherein the second and the third insulating layers each comprise oxygen and are in direct contact with the oxide semiconductor layer.

11. The semiconductor device according to claim 10 ,
wherein the third insulating layer is in direct contact with the first conductive layer.

12. The semiconductor device according to claim 10 ,
wherein the fourth insulating layer is in direct contact with the first conductive layer.

13. The semiconductor device according to claim 10 ,
wherein the fourth insulating layer is on and in direct contact with a top surface of the first conductive layer.

14. The semiconductor device according to claim 10 ,
wherein the oxide semiconductor layer is electrically connected to the second conductive layer via one of the third and the fourth conductive layers.

15. The semiconductor device according to claim 10 , the first transistor further comprising:
a fifth conductive layer over the fourth insulating layer,
wherein the oxide semiconductor layer is electrically connected to the second conductive layer via the fifth conductive layer and one of the third and the fourth conductive layers.

16. The semiconductor device according to claim 10 ,
wherein the substrate is a semiconductor substrate, and
wherein the non-oxide semiconductor layer is comprised in the semiconductor substrate.

17. The semiconductor device according to claim 10 ,
wherein there is direct contact between at least the first and the second insulating layers, between the second and the third insulating layers, or between the third and the fourth insulating layers.

18. The semiconductor device according to claim 10 , wherein the oxide semiconductor layer is formed from an In—Ga—Zn—O-based oxide semiconductor material.

19. A memory element comprising the semiconductor device according to claim 10 .

20. An electronic appliance comprising the semiconductor device according to claim 10 .

21. A semiconductor device comprising:
a substrate;
a second transistor comprising:
a second channel formation region including a non-oxide semiconductor layer;
a second conductive layer overlapping with the second channel formation region; and
a fifth insulating layer between the non-oxide semiconductor layer and the second conductive layer;

first to fourth insulating layers stacked in this order over the second channel formation region and over the second conductive layer; and
a first transistor, the first transistor comprising:
a first channel formation region including an oxide semiconductor layer between the second and the third insulating layers;
a first conductive layer over the third insulating layer and overlapping with the first channel formation region; and
third and fourth conductive layers on and in direct contact with the oxide semiconductor layer and below the third insulating layer;

wherein the first and the fourth insulating layers each comprise aluminum and oxygen; and
wherein the second and the third insulating layers each comprise silicon and oxygen.

22. The semiconductor device according to claim 21 ,
wherein the second and the third insulating layers are in direct contact with the oxide semiconductor layer.

23. The semiconductor device according to claim 21 ,
wherein the fourth insulating layer is in direct contact with the first conductive layer.

24. The semiconductor device according to claim 21 ,
wherein the fourth insulating layer is on and in direct contact with a top surface of the first conductive layer.

25. The semiconductor device according to claim 21 ,
wherein the oxide semiconductor layer is electrically connected to the second conductive layer via one of the third and the fourth conductive layers.

26. The semiconductor device according to claim 21 , the first transistor further comprising:
a fifth conductive layer over the fourth insulating layer,
wherein the oxide semiconductor layer is electrically connected to the second conductive layer via the fifth conductive layer and one of the third and the fourth conductive layers.

27. The semiconductor device according to claim 21 ,
wherein the substrate is a semiconductor substrate, and
wherein the non-oxide semiconductor layer is comprised in the semiconductor substrate.

28. The semiconductor device according to claim 21 ,
wherein there is direct contact between at least the first and the second insulating layers, between the second and the third insulating layers, or between

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Koyama Jun
• Kato Kiyoshi

Classifications

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3426

  Oxides · CPC title

• H10P14/22

  using physical deposition, e.g. vacuum deposition or sputtering · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title