Carrier substrate and method for producing semiconductor chips

Patent metadata

Field	Value
Publication number	US-9704945-B2
Application number	US-201213984081-A
Country	US
Kind code	B2
Filing date	Feb 7, 2012
Priority date	Feb 16, 2011
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A carrier substrate includes a first major face and a second major face opposite the first major face. A diode structure is formed between the first major face and the second major face, which diode structure electrically insulates the first major face from the second major face at least with regard to one polarity of an electrical voltage.

First claim

The invention claimed is:

1. A semiconductor chip comprising a semiconductor body with a semiconductor layer sequence and a carrier with a first major face and a second major face opposite the first major face, the semiconductor body arranged on the first major face and a diode structure formed between the first major face and the second major face, wherein
the diode structure electrically insulates the first major face from the second major face at least with regard to one polarity of an electrical voltage,
the diode structure extends over an entire lateral extent of the carrier;
the semiconductor layer sequence comprises an active region that generates radiation;
the active region is electrically insulated from the second major face by the diode structure,
the semiconductor body comprises a radiation exit face facing away from the carrier,
the entire radiation exit face is free of electrical contacts,
the semiconductor body is cohesively bonded to the carrier by a bonding layer arranged between the first major face and the semiconductor body, and
a protection diode is formed in the carrier and arranged between the first major face and the diode structure.

2. The semiconductor chip according to claim 1 , wherein the diode structure electrically insulates the first major face from the second major face with regard to both polarities.

3. The semiconductor chip according to claim 1 , wherein the diode structure comprises a first diode and a second diode, the first diode and the second diode being oppositely oriented with regard to their conducting direction.

4. The semiconductor chip according to claim 1 , wherein the carrier contains a semiconductor material.

5. The semiconductor chip according to claim 1 , wherein the diode structure is formed by layered doping of the carrier.

6. The semiconductor chip according to claim 1 , wherein the diode structure comprises at least three successive layers configured alternately with regard to their conduction type.

7. The semiconductor chip according to claim 1 , wherein the carrier is cohesively bonded to the semiconductor layer sequence.

8. The semiconductor chip according to claim 1 , wherein a side face of the carrier is provided with a passivation layer.

9. The semiconductor chip according to claim 1 , further comprising a first contact and a second contact arranged on a side of the carrier facing away from the second major face and adapted to receive an external electrical voltage.

10. The semiconductor chip according to claim 9 , wherein the first contact, the second contact and the semiconductor body are arranged side by side on the carrier.

11. The semiconductor chip according to claim 1 , wherein
an insulation layer is arranged on the first major surface;
the protection diode comprises a first sub-region and a second sub-region that differ from one another with regard to conduction type;
the insulation layer comprises a first opening and a second opening; and
the first opening overlaps the first sub-region and the second opening overlaps the second sub-region.

12. A semiconductor chip comprising a semiconductor body with a semiconductor layer sequence and a carrier, a first major face, a second major face opposite the first major face and a side face provided with a radiation-opaque passivation layer, the semiconductor body arranged on the first major face and a diode structure formed between the first major face and the second major face, wherein
the diode structure electrically insulates the first major face from the second major face at least with regard to one polarity of an electrical voltage,
the side face is an outer side face of the carrier delimiting the extent of the carrier in a lateral direction and the radiation-opaque layer completely covers the side face,
the diode structure extends over an entire lateral extent of the carrier;
the semiconductor layer sequence comprises an active region that generates radiation;
the active region is electrically insulated from the second major face by the diode structure;
a protection diode is formed in the carrier and arranged between the first major face and the diode structure;
the protection diode is formed by a first sub-region and a second sub-region that differ from one another with regard to conduction type;
in a plan view of the semiconductor chip, the second sub-region is completely surrounded by the first sub-region; and
the first sub-region has a smaller lateral extent than the diode structure.

13. The semiconductor chip according to claim 12 , wherein the active region and the protection diode are interconnected in antiparallel with regard to their conducting direction.

Assignees

• Günther Ewald Karl Michael
• Plöβl Andreas
• Zull Heribert
• Veit Thomas
• Kämpf Mathias
• Dennemarck Jens
• Böhm Bernd
• Perzlmaier Korbinian
• Osram Opto Semiconductors Gmbh

Inventors

• Günther Ewald Karl Michael
• Plöβl Andreas
• Zull Heribert
• Veit Thomas
• Kämpf Mathias
• Dennemarck Jens
• Böhm Bernd
• Perzlmaier Korbinian

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/547

  Dispositions of multiple bond wires · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title