Dual-layer dielectric in memory device

Patent metadata

Field	Value
Publication number	US-9704923-B1
Application number	US-201514998194-A
Country	US
Kind code	B1
Filing date	Dec 23, 2015
Priority date	Dec 23, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a memory array comprising a plurality of wordlines and a plurality of bitlines; and
fill regions between respective pairs of adjacent wordlines of the plurality of wordlines, wherein one or more of the fill regions includes a first dielectric material and a second dielectric material disposed on the first dielectric material, wherein the plurality of bitlines is disposed on the second dielectric material, wherein the first dielectric material comprises an organic spin-on dielectric material (CSOD), and wherein the second dielectric material comprises a second dielectric material that is different from the first dielectric material.

2. The apparatus of claim 1 , wherein the second dielectric material comprises one or more of an inorganic dielectric material or alkoxide compound material.

3. The apparatus of claim 2 , wherein the alkoxide compound material includes tetraethyl orthosilicate (TEOS).

4. The apparatus of claim 1 , wherein individual wordlines of the plurality of wordlines comprise a cell stack comprising a top electrode layer, wherein a lower surface of the second dielectric material is about at or below a level of a lower surface of the top electrode layer.

5. The apparatus of claim 4 , wherein the cell stack comprises a selector device layer and a storage device layer.

6. An apparatus comprising:
a memory array comprising a plurality of wordlines;
fill regions between respective pairs of adjacent wordlines of the plurality of wordlines, wherein one or more of the fill regions includes a first dielectric material and a second dielectric material disposed on the first dielectric material, wherein the first dielectric material comprises an organic spin-on dielectric material (CSOD), and wherein the second dielectric material comprises a second dielectric material that is different from the first dielectric material; and a sealing layer coupled to a side surface of the wordlines, wherein a portion of the second dielectric material is disposed on the sealing layer.

7. An apparatus comprising:
a memory array comprising a plurality of wordlines;
fill regions between respective pairs of adjacent wordlines of the plurality of wordlines, wherein one or more of the fill regions includes a first dielectric material and a second dielectric material disposed on the first dielectric material, wherein the first dielectric material comprises an organic spin-on dielectric material (CSOD), and wherein the second dielectric material comprises a second dielectric material that is different from the first dielectric material, wherein the memory array further comprises a peripheral portion adjacent to the plurality of wordlines, wherein the peripheral portion includes:
the first dielectric material;
the second dielectric material disposed on the first dielectric material; and
one or more vias disposed through the first and second dielectric materials to provide electrical connectivity for the memory array with circuitry associated with the memory array.

8. The apparatus of claim 1 , wherein the memory array comprises a three-dimensional (3D) memory array.

Assignees

• Intel Corp

Inventors

• Bernhardt Michael J
• Kim Yudong
• Frost Denzil S
• Allen Iii Tuman Earl
• Baker Kevin Lee
• Yastrebenetsky Kolya
• Weimer Ronald Allen

Classifications

• H10P50/287

  by chemical means · CPC title

• H10W90/725

  between a chip and a laterally-adjacent insulating package substrate, interposer or RDL · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/242

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title