Semiconductor device having a memory cell and method of forming the same

Patent metadata

Field	Value
Publication number	US-9704871-B2
Application number	US-201514840459-A
Country	US
Kind code	B2
Filing date	Aug 31, 2015
Priority date	Sep 18, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

There is provided an apparatus includes a substrate having a main surface, a wordline buried in the substrate and a bitline buried in a shallower area than the wordline in the substrate.

First claim

I claim:

1. A device comprising:
a semiconductor substrate having a main surface;
a first wordline buried in the semiconductor substrate;
a first bitline buried in the semiconductor substrate between the first wordline and the main surface of the semiconductor substrate;
a first transistor including a gate, a source and a drain; the gate being electrically connected to the first wordline, and one of the source and drain being electrically connected to the first bitline;
a first memory element formed over the main surface of the semiconductor substrate and electrically connected to the other of the source and drain;
a bitline trench provided over the first wordline, wherein the first bitline is buried in the bitline trench; and
wherein each of the bitline trench and the first bitline has a snake shape pattern and elongates in a direction substantially vertical to a first direction in which the first wordline elongates.

2. The device of claim 1 , further comprising bitline spacers each covering a corresponding one of side surfaces of the first bitline.

3. The device of claim 2 , wherein each of the bitline spacers comprises a silicon oxide film.

4. The device of claim 2 , wherein each of the bitline spacers comprises an air gap.

5. The device of claim 2 , wherein an upper surface of each of the bitline spacers and an upper surface of the first bitline are substantially coplanar with each other.

6. The device of claim 5 , wherein a portion of the bitline trench between the main surface of the semiconductor substrate and each of the upper surfaces of the bitline spacers is filled with a cap dielectric film.

7. The device of claim 1 , wherein the other of the source and drain is formed such that the first wordline is sandwiched between the one of the source and drain and the other of the source and drain, and the first memory element is connected to an upper surface of the other of the source and drain of the first transistor.

8. The device of claim 7 , wherein the first memory element comprises a lower electrode, a capacitor dielectric film covering the lower electrode and an upper electrode covering the capacitor dielectric film, the lower electrode is directly connected to the upper surface of the other of the source and drain of the first transistor.

9. The device of claim 7 , wherein the upper surface of the other of the source and drain of first transistor is substantially coplanar with the main surface of the semiconductor substrate, the upper surface of the one of the source and drain of the first transistor being formed at a lower position than the main surface of the semiconductor substrate and at a higher position than an upper surface of the first wordline.

10. The device of claim 1 , further comprising an active area defined by a first isolation dielectric film extending in a first direction and a second isolation dielectric film extending in a second direction crossing the first direction, the first wordline elongating in the first direction so as to cross the active area, the first transistor is formed within the active area.

11. The device of claim 10 , wherein an etching rate of the first isolation dielectric film is less than that of the second isolation dielectric film.

12. The device of claim 11 , wherein the first isolation dielectric film comprises a silicon nitride film and the second isolation dielectric film comprises a silicon oxide film.

Assignees

• Micron Technology Inc

Inventors

• Wu Nan

Classifications

• H01L27/10814 Primary

  Electricity · mapped topic

• H01L27/10876

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H01L27/10885

  Electricity · mapped topic

• H10D89/10

  Integrated device layouts · CPC title