Nanotube structure based metal damascene process

Patent metadata

Field	Value
Publication number	US-9704800-B2
Application number	US-201514836978-A
Country	US
Kind code	B2
Filing date	Aug 27, 2015
Priority date	Jan 30, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include forming a plurality of groups of nanotubes over a substrate, wherein the groups of nanotubes may be arranged such that a portion of the substrate is exposed and forming metal over the exposed portion of the substrate between the plurality of groups of nanotubes.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a first layer provided on the substrate, wherein the first layer comprises aluminum; and
a second layer provided on the first layer, wherein the second layer comprises one of iron, cobalt, and nickel,
a plurality of groups of nanotubes arranged over the substrate and disposed over the second layer, the plurality of groups of nanotubes spaced apart from each other so as to define one or more trenches therebetween, wherein each of the plurality of groups of nanotubes comprises a plurality of nanotubes;
metal formed over the substrate between the plurality of groups of nanotubes, the metal completely filling the one or more trenches between the plurality of groups of nanotubes.

2. The semiconductor device of claim 1 ,
wherein each group of nanotubes comprises insulating material between the nanotubes.

3. The semiconductor device of claim 2 , wherein the insulating material extends from a top end to a bottom end of the nanotubes.

4. The semiconductor device of claim 1 , wherein the metal is formed directly on the substrate.

5. The semiconductor device of claim 1 , wherein each of the plurality of groups of nanotubes is aligned substantially vertically upright with respect to a surface of the substrate.

6. The semiconductor device of claim 5 , wherein each of the plurality of groups of nanotubes has substantially the same height from the surface of the substrate.

7. The semiconductor device of claim 6 , wherein a top surface of the metal is at approximately a same height level as the plurality of groups of nanotubes.

8. The semiconductor device of claim 1 ,
wherein the plurality of groups of nanotubes comprise carbon nanotubes.

9. The semiconductor device of claim 2 , wherein the insulating material comprises an oxide or a silicon nitride.

10. The semiconductor device of claim 9 , wherein the oxide is silicon oxide or titanium oxide.

11. The semiconductor device of claim 1 , wherein the metal formed over the substrate between the plurality of groups of nanotubes is copper.

12. The semiconductor device of claim 1 , wherein each spacing between the nanotubes of each group of the plurality of groups of nanotubes is less than each spacing between the plurality of groups of nanotubes.

Assignees

• Infineon Technologies Ag

Inventors

• Joshi Ravi
• Steinbrenner Juergen

Classifications

• H10P14/274

  using seed materials · CPC title

• H10P50/287

  by chemical means · CPC title

• H10P14/6902

  composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon · CPC title

• H10P14/3464

  Nanotubes · CPC title

• H10P14/3406 Primary

  Carbon, e.g. diamond-like carbon · CPC title