Power semiconductor module

Patent metadata

Field	Value
Publication number	US-9704768-B2
Application number	US-201315021836-A
Country	US
Kind code	B2
Filing date	Dec 17, 2013
Priority date	Dec 17, 2013
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

It is an object of the present invention to achieve reduced faults in manufacturing steps and increased reliability by relieving electric field strength of a surface of a power semiconductor chip. The present invention includes: a power semiconductor chip disposed on an insulating substrate; wiring connected to a surface conductor pattern in an element region of the power semiconductor chip; a low dielectric constant film disposed between the wiring and the peripheral region; and a sealing material formed so as to cover the insulating substrate, the power semiconductor chip, the wiring, and the low dielectric constant film. The low dielectric constant film has a dielectric constant lower than that of the sealing material.

First claim

The invention claimed is:

1. A power semiconductor module, comprising:
an insulating substrate;
a power semiconductor chip disposed on said insulating substrate;
said insulating substrate having a surface on which an upper electrode is formed,
said power semiconductor chip having a surface on which a surface conductor pattern is formed,
said power semiconductor chip having a back surface on which a back-surface conductor pattern is formed,
said power semiconductor chip having the surface in which an element region and a peripheral region surrounding said element region in plan view are defined,
said upper electrode on said insulating substrate and said back-surface conductor pattern on said power semiconductor chip being connected to each other with solder therebetween,

wiring connected to said surface conductor pattern in said element region of said power semiconductor chip;
a low dielectric constant film disposed between said wiring and said peripheral region and only above said surface of said power semiconductor chip; and
a sealing material formed so as to cover said insulating substrate, said power semiconductor chip, said wiring, and said low dielectric constant film,
wherein said low dielectric constant film has a dielectric constant lower than that of said sealing material, and
said low dielectric constant film is formed so as to cover only a part of said peripheral region of the surface of said power semiconductor chip overlapping a wiring path of said wiring in plan view.

2. A power semiconductor module, comprising:
an insulating substrate;
a power semiconductor chip disposed on said insulating substrate;
said insulating substrate having a surface on which an upper electrode is formed,
said power semiconductor chip having a surface on which a surface conductor pattern is formed,
said power semiconductor chip having a back surface on which a back-surface conductor pattern is formed,
said power semiconductor chip having the surface in which an element region and a peripheral region surrounding said element region in plan view are defined,
said upper electrode on said insulating substrate and said back-surface conductor pattern on said power semiconductor chip being connected to each other with solder therebetween,

wiring connected to said surface conductor pattern in said element region of said power semiconductor chip;
a low dielectric constant film disposed between said wiring and said peripheral region; and
a sealing material formed so as to cover said insulating substrate, said power semiconductor chip, said wiring, and said low dielectric constant film,
wherein said low dielectric constant film has a dielectric constant lower than that of said sealing material, and
said low dielectric constant film is formed so as to cover only a surface of said wiring.

Assignees

• Mitsubishi Electric Corp

Inventors

• Kawaguchi Yasuto

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W72/01515

  Forming coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title