Substrate Design with Balanced Metal and Solder Resist Density
US-2015130050-A1 · May 14, 2015 · US
Dual side solder resist layers for coreless packages and packages with an embedded interconnect bridge and their methods of fabrication
US9704735B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9704735-B2 |
| Application number | US-201414463285-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 19, 2014 |
| Priority date | Aug 19, 2014 |
| Publication date | Jul 11, 2017 |
| Grant date | Jul 11, 2017 |
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Abstract
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A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.
First claim
Opening claim text (preview).
What is claimed is: 1. A package substrate, comprising: a build-up structure comprising at least one insulating layer, at least one via, and at least one conductive layer; a first plurality of contact pads in a first side of the build-up structure, the first plurality of contact pads each having an external surface co-planar with the first side of the build-up structure; a second plurality of contact pads on a second side of the build-up structure opposite of the first side;…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9704735B2 cover?
- A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom …
- Who is the assignee on this patent?
- Konchady Manohar S, Wu Tao, Roy Mihir K, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification H10P72/74. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jul 11 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).