Reducing SRAM power using strategic data pattern storage

Patent metadata

Field	Value
Publication number	US-9704568-B1
Application number	US-201615256396-A
Country	US
Kind code	B1
Filing date	Sep 2, 2016
Priority date	Sep 2, 2016
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

Embodiments herein describe a SRAM that selectively flips received chunks of data from a high power state to a low power state before storing the chunks of data. The SRAM generates a flip bit for each of the data chunks stored in memory. The state of the flip bit varies depending on whether the corresponding data chunk was flipped before being stored in the SRAM. In one embodiment, the SRAM flips the bits in a data chunk before storing the bits only if all the bits are in the high power state. If so, the SRAM sets the flip bit for the data chunk to a first state and changes all the bits to the low power state before storing the data chunk. If not, the SRAM sets the flip bit to a second state and stores the data chunk without changing the states of the bits.

First claim

What is claimed is:

1. A static random-access memory (SRAM), comprising:
a data driver configured to:
generate a flip bit indicating whether a plurality of bits in a received data chunk are in a high power state,
upon determining the plurality of bits are in the high power state, store the flip bit in the SRAM in a first state and flip the plurality of bits before storing the plurality of bits in the SRAM, and
upon determining at least one of the plurality of bits is in a low power state, store the flip bit in the SRAM in a second state different from the first state and store the plurality of bits in the SRAM without flipping any of the plurality of bits.

2. The SRAM of claim 1 , the data driver comprising:
a NAND gate configured to receive the plurality of bits and output a signal indicating whether all of the plurality of bits are in the high power state.

3. The SRAM of claim 2 , the data driver comprising:
an inverter coupled to the output of the NAND gate, the inverter configured to output the flip bit in the first state if all the plurality of bits are in the high power state and output the flip bit in the second state if at least one of the plurality of bits is in the low power state, wherein the first state corresponds to the high power state and the second state corresponds to the low power state.

4. The SRAM of claim 2 , the data driver comprising:
a plurality of NAND gates, wherein each of the plurality of NAND gates is configured to receive the signal of the NAND gate and a respective one of the plurality of bits.

5. The SRAM of claim 4 , the data driver comprising:
a plurality of inverters each coupled to a respective output of one of the plurality of NAND gates, wherein outputs of the plurality of inverters are flipped relative to the plurality of bits if all of the plurality of bits are in the high power state.

6. The SRAM of claim 1 , wherein a stored bit in the SRAM that is in the high power state requires more power to read out than when the stored bit is in the low power state.

7. The SRAM of claim 1 , further comprising:
readout circuitry configured to:
retrieve stored data corresponding to the received data chunk,
retrieve the flip bit,
upon determining the flip bit is in the first state, flipping each bit of the stored data before transmitting the stored data to a requesting entity, and
upon determining the flip bit is in the second state, transmitting the stored data to the requesting entity without flipping any bits of the stored data.

8. An integrated circuit, comprising:
a data driver for a SRAM configured to:
generate a flip bit indicating whether a plurality of bits in a received data chunk are in a high power state,
upon determining the plurality of bits are in the high power state, store the flip bit in the SRAM in a first state and flip the plurality of bits before storing the plurality of bits in the SRAM, and
upon determining at least one of the plurality of bits is in a low power state, store the flip bit in the SRAM in a second state different from the first state and store the plurality of bits in the SRAM without flipping any of the plurality of bits.

9. The integrated circuit of claim 8 , the data driver comprising:
a NAND gate configured to receive the plurality of bits and output a signal indicating whether all of the plurality of bits are in the high power state.

10. The integrated circuit of claim 9 , the data driver comprising:
an inverter coupled to the output of the NAND gate, the inverter configured to output the flip bit in the first state if all the plurality of bits are in the high power state and output the flip bit in the second state if at least one of the plurality of bits is in the low power state, wherein the first state corresponds to the high power state and the second state corresponds to the low power state.

11. The integrated circuit of claim 9 , the data driver comprising:
a plurality of NAND gates, wherein each of the plurality of NAND gates is configured to receive the signal of the NAND gate and a respective one of the plurality of bits.

12. The integrated circuit of claim 11 , the data driver comprising:
a plurality of inverters each coupled to a respective output of one of the plurality of NAND gates, wherein outputs of the plurality of inverters are flipped relative to the plurality of bits if all of the plurality of bits are in the high power state.

13. The integrated circuit of claim 8 , wherein a stored bit in the SRAM that is in the high power state requires more power to read out than when the stored bit is in the low power state.

14. The integrated circuit of claim 8 , further comprising:
readout circuitry configured to:
retrieve stored data corresponding to the received data chunk,
retrieve the flip bit,
upon determining the flip bit is in the first state, flipping each bit of the stored data before transmitting the stored data to a requesting entity, and
upon determining the flip bit is in the second state, transmitting the stored data to the requesting entity without flipping any bits of the stored data.

15. A method for operating an SRAM, comprising:
generating a first flip bit indicating whether a first plurality of bits in a first received data chunk are in a high power state;
upon determining the first plurality of bits are in the high power state:
storing the first flip bit in the SRAM in a first state, and
flipping the first plurality of bits before storing the first plurality of bits in the SRAM;

generating a second flip bit indicating whether a second plurality of bits in a second received data chunk are in the high power state; and
upon determining at least one of the second plurality of bits is in a low power state:
storing the second flip bit in the SRAM in a second state different from the first state, and
storing the second plurality of bits in the SRAM without flipping any of the second plurality of bits.

16. The method of claim 15 , further comprising:
receive the first plurality of bits at a NAND gate that outputs a signal indicating whether all of the plurality of bits are in the high power state.

17. The method of claim 16 , further comprising:
receiving the output signal of the NAND gate at an inverter that outputs the first flip bit and the second flip bit.

18. The method of claim 16 , further comprising:
receiving the output signal of the NAND gate and a respective one of the first plurality of bits at a plurality of NAND gates.

19. The method of claim 15 , wherein a stored bit in the SRAM that is in the high power state requires more power to read out than when the stored bit is in the low power state.

20. The method of claim 15 , further comprising:
retrieving stored data corresponding to the first received data chunk;
retrieving the first flip bit; and
upon determining the first flip bit is in the first state, flipping each bit of the stored data before transmitting the stored data to a requesting entity.

Assignees

• IBM

Inventors

• Lee Michael J
• Wang Geoffrey

Classifications

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C11/413

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title