Organic light emitting diode pixel compensation circuit, and display panel and display device containing the same

Patent metadata

Field	Value
Publication number	US-9704435-B2
Application number	US-201414536492-A
Country	US
Kind code	B2
Filing date	Nov 7, 2014
Priority date	Jun 23, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

An Organic Light Emitting Diode pixel compensation circuit is disclosed. The circuit includes first through fifth transistors, and a storage capacitor. The first transistor is coupled to a first scan signal, a power supply voltage, and a first electrode of the storage capacitor. In addition, the second transistor is coupled to the first scan signal, a data signal, and the third transistor. The third transistor is coupled to the power supply voltage, and the fifth transistor. Furthermore, the fourth transistor is coupled to a second scan signal, the third transistor, and the storage capacitor, and fifth transistor is coupled to a light emitting signal, and the OLED. In addition, the storage capacitor is coupled to the fifth transistor, and a low-level signal and emits light based on a drive current generated by the third transistor.

First claim

What is claimed is:

1. An Organic Light Emitting Diode (OLED) pixel compensation circuit, configured to drive an OLED to emit light, the OLED pixel compensation circuit comprising:
first, second, third, fourth, and fifth transistors; and
a storage capacitor,
wherein a gate electrode of the first transistor is directly electrically connected to a first scan signal, a first electrode of the first transistor is directly electrically connected to a power supply voltage, and a second electrode of the first transistor is directly electrically connected to a first electrode of the storage capacitor,
wherein a gate electrode of the second transistor is directly electrically connected to the first scan signal, a first electrode of the second transistor is directly electrically connected to a data signal, and a second electrode of the second transistor is directly electrically connected to a gate electrode of the third transistor,
wherein a first electrode of the third transistor is directly electrically connected to the power supply voltage, and a second electrode of the third transistor is directly electrically connected to a first electrode of the fifth transistor,
wherein a gate electrode of the fourth transistor is directly electrically connected to a second scan signal, a first electrode of the fourth transistor is directly electrically connected to the gate electrode of the third transistor, and a second electrode of the fourth transistor is directly electrically connected to the first electrode of the storage capacitor, and the fourth transistor is configured to transfer the data signal received by the first electrode of the fourth transistor to the first electrode of the storage capacitor in response to the second scan signal,
wherein a gate electrode of the fifth transistor is directly electrically connected to a light emitting signal, and a second electrode of the fifth transistor is directly electrically connected to a first electrode of the OLED,
wherein a second electrode of the storage capacitor is directly electrically connected to the first electrode of the fifth transistor, and
wherein a second electrode of the OLED is directly electrically connected to a low-level signal and emits light based on a drive current generated by the third transistor.

2. The circuit according to claim 1 , wherein:
the first transistor is configured to transfer the power supply voltage to the first electrode of the storage capacitor in response to the first scan signal;
the second transistor is configured to transfer the data signal to the gate electrode of the third transistor in response to the first scan signal;
the third transistor is configured to generate the drive current in response to the power supply voltage and a gate voltage of the third transistor;
the fifth transistor is configured to transfer a voltage of the first electrode of the fifth transistor to the second electrode of the fifth transistor in response to the light emitting signal; and
the storage capacitor is configured to store a received voltage and couple a change value of a voltage on the second electrode of the storage capacitor to the first electrode of the storage capacitor.

3. The circuit according to claim 1 , wherein the third transistor, the fourth transistor and the fifth transistor are N-type Metal Oxide Semiconductor (NMOS) transistors.

4. The circuit according to claim 3 , wherein the first transistor and the second transistor are NMOS transistors or are P-type Metal Oxide Semiconductor (PMOS) transistors.

5. The circuit according to claim 4 , wherein the first transistor and the second transistor are PMOS transistors, and the second scan signal is the same as the first scan signal.

6. The circuit according to claim 4 , wherein the first transistor and the second transistor are NMOS transistors, and a process of pixel compensation comprises a first stage, a second stage and a third stage, wherein:
during the first stage, the first scan signal is a high-level signal, the second scan signal is a low-level signal, the light emitting signal is a high-level signal, and the data signal is a high-level signal,
during the second stage, the first scan signal is a high-level signal, the second scan signal is a low-level signal, the light emitting signal is a low-level signal, and the data signal comprises a high-level signal,
during the third stage, the first scan signal is a low-level signal, the second scan signal is a high-level signal, and the light emitting signal is a high-level signal.

7. The circuit according to claim 5 , wherein a process of pixel compensation comprises a first stage, a second stage and a third stage, wherein:
during the first stage, the first scan signal is a low-level signal, the light emitting signal is a high-level signal, and the data signal is a high-level signal,
during the second stage, the first scan signal is a low-level signal, the light emitting signal is a low-level signal, and the data signal is a high-level signal, and
during the third stage, the first scan signal is a high-level signal and the light emitting signal is a high-level signal.

8. The circuit according to claim 6 , wherein the first stage is a reset stage of the circuit, and the circuit is reset during the first stage.

9. The circuit according to claim 7 , wherein the first stage is a reset stage of the circuit, and the circuit is reset during the first stage.

10. The circuit according to claim 6 , wherein the second stage is a threshold compensation stage of the third transistor in the circuit, and a threshold voltage of the third transistor is captured during the second stage.

11. The circuit according to claim 7 , wherein the second stage is a threshold compensation stage of the third transistor in the circuit, and a threshold voltage of the third transistor is captured during the second stage.

12. The circuit according to claim 6 , wherein the third stage is a light emitting stage of the circuit, and the OLED is driven to emit light during the third stage.

13. The circuit according to claim 7 , wherein the third stage is a light emitting stage of the circuit, and the OLED is driven to emit light during the third stage.

14. A display panel, comprising an Organic Light Emitting Diode (OLED) pixel compensation circuit, configured to drive an OLED to emit light, the OLED pixel compensation circuit comprising:
first, second, third, fourth, and fifth transistors; and
a storage capacitor,
wherein a gate electrode of the first transistor is directly electrically connected to a first scan signal, a first electrode of the first transistor is directly electrically connected to a power supply voltage, and a second electrode of the first transistor is directly electrically connected to a first electrode of the storage capacitor,
wherein a gate electrode of the second transistor is directly electrically connected to the first scan signal, a first electrode of the second transistor is directly electrically connected to a data signal, and a second electrode of the second transistor is directly electrically connected to a gate electrode of the third transistor,
wherein a first electrode of the third transistor is directly electrically connected to the power supply voltage, and a second electrode of the third transistor is directly electrically connected to a first electrode of the fifth transistor,
wherein a gate electrode of the fourth transistor is directly electrically connected to a second scan signal, a first electrode of the fourth transistor is directly electrically connected to the gate electrode of the third transistor, and a second electrode of the fourt

Assignees

• Shanghai Tianma Am-Oled Co Ltd
• Tianma Microelectronics Co Ltd
• Shanghai Tianma Am-Oled Co Ltd

Inventors

• Chen Dan
• Qian Dong

Classifications

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2310/0251

  Precharge or discharge of pixel before applying new pixel voltage · CPC title

• G09G2320/045

  Compensation of drifts in the characteristics of light emitting or modulating elements · CPC title