Cryptographic support instructions

Patent metadata

Field	Value
Publication number	US-9703966-B2
Application number	US-201514792796-A
Country	US
Kind code	B2
Filing date	Jul 7, 2015
Priority date	Nov 17, 2011
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A data processing system includes a single instruction multiple data register file and single instruction multiple processing circuitry. The single instruction multiple data processing circuitry supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.

First claim

We claim:

1. Data processing apparatus comprising:
a single instruction multiple data register file; and
single instruction multiple data processing circuitry coupled to said single instruction multiple data register file and configured to be controlled by a single instruction multiple data program instruction to perform a processing operation independently upon separate data elements stored within separate lanes within an input operand register of said single instruction multiple data register file; wherein
said single instruction multiple data processing circuitry is configured to be controlled by a first further program instruction and a second further program instruction to perform a further processing operation upon an input digest data value to generate an output digest data value, the first further program instruction being operable to generate, in dependence on said input digest data value, a first output operand representative of a first portion of the output digest data value, the second further program instruction being operable to generate, in dependence on said input digest data value, a second output operand representative of a remaining portion of the output digest data value,
wherein the input digest data value comprises a sequence of data elements held within said single instruction multiple data register file, said first portion and said remaining portion of the output digest data value being dependent upon all data elements within said sequence of data elements, wherein said first portion and said remaining portion represent portions of different significance within the output digest data value, and
wherein said further processing operation is an iterative processing operation consuming successive words of data and at least portions of intermediate hash values to generate an output hash value.

2. Data processing apparatus as claimed in claim 1 , wherein said further processing operation is a cryptographic processing operation.

3. Data processing apparatus as claimed in claim 1 , wherein said first further program instruction has a first input operand Qd[ 127 : 0 ] and a second input operand Sn[ 31 : 0 ] both read from said single instruction multiple data register file and a vector data value comprising Vm[32*2 N −1: 0 ], where N is a positive integer, said further processing operation producing said output operand Qd output [ 127 : 0 ] to have a value the same as given by the steps:

X[127:0] = Qd[127:0];

Y[31:0] = Sn[31:0];

for (I = 0 to (2 N −1));

   {

      Index = (I*32);

      t1[31:0] = OP FUNC (X[63:32], X[95:64], X[127:96]);

      Y[31:0] = Y[31:0] + ROL(X[31:0], 5) + T1[31:0] +

      Vm[Index+31:Index];

      X[63:32] = ROL(X[63:32], 30);

      T2[31:0] = Y[31:0];

      Y[31:0] = X[127:96];

      X[127:0] = {X[95:0]:T2[31:0]}

   }

Qd output [127:0] = X[127:0];

where OP FUNC (B, C, D) is one of:
(((C XOR D) AND B) XOR D);
(B XOR C XOR D); and
(B AND C) OR ((B OR C) AND D); and
ROL (P, Q) is a left rotate of value P by Q bit positions.

4. Data processing apparatus as claimed in claim 3 , wherein said first further program instruction includes a field selecting as OP FUNC (B, C, D) one of:
(((C XOR D) AND B) XOR D);
(B XOR C XOR D); and
(B AND C) OR ((B OR C) AND D).

5. Data processing apparatus as claimed in claim 3 , wherein said first input operand Qd[ 127 : 0 ] and said second input operand Sn[ 31 : 0 ] are read from separate registers within said single instruction multiple data register file.

6. Data processing apparatus as claimed in claim 3 , wherein said first input operand Qd[ 127 : 0 ] and said second input operand Sn[ 31 : 0 ] are read from a shared register within said single instruction multiple data register file.

7. Data processing apparatus as claimed in claim 3 , wherein said single instruction multiple data processing circuitry is configured to be controlled by a first schedule update instruction having a first input operand sp[ 127 : 0 ] and a second input operand Sq[ 127 : 0 ] and generating an output operand Sr[ 127 : 0 ] with a value the same as given by the steps:

T[127:0] = {Sp[63:0]:Sq[127:64]} and

Sr[127:0] = T[127:0] XOR Sr[127:0] XOR Sq[127:0].

8. Data processing apparatus as claimed in claim 1 , wherein said second further program instruction has a first input operand Qd[ 127 : 0 ] and a second input operand Sn[ 31 : 0 ] both read from said single instruction multiple data register file and a vector data value comprising Vm[32*2 N −1:0], where N is a positive integer, said further processing operation producing said output operand Qd output [ 127 : 0 ] to have a value the same as given by the steps:

X[127:0] = Qd[127:0];

Y[31:0] = Sn[31:0];

for (I = 0 to (2 N −1));

   {

      Index = (I * 32);

      T1[31:0] = OP_FUNC(X[63:32], X[95:64], X[127:96]);

      Y  = Y + ROL(X[31:0], 5) + T1[31:0] + Vm[(Index +

      31):Index];

      X[63:32] = ROL(X[63:32], 30);

      T2[31:0] = Y;

      Y  = X[127:96];

      X[127:0] = {X[95:0]:T2[31:0]};

   }

Qd output [127:0] = {0:Y[31:0]};

where OP FUNC (B, C, D) is one of:
(((C XOR D) AND B) XOR D);
(B XOR C XOR D); and
(B AND C) OR ((B OR C) AND D); and
ROL (P, Q) is a left rotate of value P by Q bit positions.

9. Data p

Assignees

• Advanced Risc Mach Ltd

Inventors

• Horsnell Matthew James
• Grisenthwaite Richard Roy
• Biles Stuart David
• Kershaw Daniel

Classifications

• H04L2209/125

  Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• H04L9/3239

  involving non-keyed hash functions, e.g. modification detection codes [MDCs], MD5, SHA or RIPEMD · CPC title

• H04L9/3236

  using cryptographic hash functions · CPC title

• H04L9/0643

  Hash functions, e.g. MD5, SHA, HMAC or f9 MAC · CPC title