Streaming, at-speed debug and validation architecture

Patent metadata

Field	Value
Publication number	US-9703916-B2
Application number	US-201414473914-A
Country	US
Kind code	B2
Filing date	Aug 29, 2014
Priority date	Jan 31, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

This application discloses a computing system implementing tools and mechanisms that can incorporate a validation system into a circuit design. The validation system can be configured to monitor at least a portion of an electronic device described in the circuit design. The tools and mechanisms can identify one or more trace signals associated with the electronic device to route to the validation system, and identify one or more trigger signals associated with the electronic device to route to the validation system. The tools and mechanisms can configure the validation system to detect a conditional event corresponding a state of the one or more trigger signals, and to transmit the trace signals associated with the electronic device for debugging in response to the detected conditional event.

First claim

The invention claimed is:

1. A method comprising:
incorporating, by a computing system, a validation system into a circuit design, wherein the validation system includes multiple validation devices configured to monitor at least a portion of an electronic device described in the circuit design, and wherein the validation devices are arranged in a serial pipelined configuration with each of the validation devices configured to transmit signals on each of a plurality of communication buses;
identifying, by the computing system, trace signals associated with the electronic device to route to the validation system; and
configuring, by the computing system over one of the communication buses in the serial pipelined configuration, the validation system to detect one or more conditional events from one or more trigger signals routed to the validation system from the electronic device, wherein the validation system is configured to transmit at least one of the trace signals associated with the electronic device, over another one of the communication buses in the serial pipelined configuration, for debugging in response to a detection of at least of the conditional events.

2. The method of claim 1 , wherein at least one of the conditional events corresponds to a state of the one or more trigger signals.

3. The method of claim 2 , wherein configuring the validation system to detect the conditional event further comprising providing an assert configuration to the validation system, wherein the assert configuration is configured to configure circuitry in the validation system to detect when the one or more trigger signals enter the state corresponding to the at least one of the conditional events.

4. The method of claim 3 , wherein providing the assert configuration to the validation system further comprising transmitting the assert configuration to a programmable logic device configured to implement the validation system and the corresponding electronic device based on the circuit design.

5. The method of claim 1 , wherein each validation device includes a trace buffer configured to store trace signals received from the electronic device, an assert logic device configured to detect at least one of the conditional events corresponding to operation of the electronic device, and a packet generator configured to transmit at least one of the trace signals stored in the trace buffer in response to the conditional event detected by the assert logic device.

6. A system comprising:
an electronic device configured to perform electrical operations; and
a validation system including multiple validation devices arranged in a serial pipelined configuration with each of the validation devices configured to transmit signals on each of a plurality of communication buses, wherein the validation system is configured to monitor trace signals associated with the electronic device, wherein the validation system is configured, over one of the communication buses in the serial pipelined configuration, to detect one or more conditional events from at least one trigger signal routed to the validation system from the electronic device, and wherein the validation system is configured to transmit, over another one of the communication buses in the serial pipelined configuration, one or more of the trace signals associated with the electronic device for debugging in response to a detection of at least of the conditional events.

7. The system of claim 6 , wherein each validation device includes a trace buffer configured to store one or more of the trace signals received from the electronic device, an assert logic device configured to detect at least one of the conditional events corresponding to operation of the electronic device, and a packet generator configured to transmit at least one of the trace signals stored in the trace buffer in response to the conditional event detected by the assert logic device.

8. The system of claim 6 , wherein the electronic device and the validation system are described in a circuit design.

9. The system of claim 6 , wherein the electronic device and the validation system are implemented in a programmable circuit device according to a circuit design.

10. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
incorporating a validation system into a circuit design, wherein the validation system includes multiple validation devices configured to monitor at least a portion of an electronic device described in the circuit design, and wherein the validation devices are arranged in a serial pipelined configuration with each of the validation devices configured to transmit signals on each of a plurality of communication buses;
identifying trace signals associated with the electronic device to route to the validation system; and
configuring, over one of the communication buses in the serial pipelined configuration, the validation system to detect one or more conditional events from one or more trigger signals routed to the validation system from the electronic device, wherein the validation system is configured to transmit at least one of the trace signals associated with the electronic device, over another one of the communication buses in the serial pipelined configuration, for debugging in response to a detection of at least of the conditional events.

11. The apparatus of claim 10 , wherein at least one of the conditional events corresponds to a state of the one or more trigger signals.

12. The apparatus of claim 10 , wherein configuring the validation system to detect the conditional event further comprising providing an assert configuration to the validation system, wherein the assert configuration is configured to configure circuitry in the validation system to detect when the one or more trigger signals enter the state corresponding to the at least one of the conditional events.

13. The apparatus of claim 12 , wherein providing the assert configuration to the validation system further comprising transmitting the assert configuration to a programmable logic device configured to implement the validation system and the corresponding electronic device based on the circuit design.

14. The apparatus of claim 10 , wherein each validation device includes a trace buffer configured to store trace signals received from the electronic device, an assert logic device configured to detect at least one of the conditional events corresponding to operation of the electronic device, and a packet generator configured to transmit at least one of the trace signals stored in the trace buffer in response to the conditional event detected by the assert logic device.

Assignees

• Mentor Graphics Corp

Inventors

• Sehgal Rajeev
• Mandavilli Srinivas
• Mathews Pradish
• Singh Ajit
• Potts Henry

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/5081 Primary

  Physics · mapped topic