Optimizing placement of circuit resources using a globally accessible placement memory

Patent metadata

Field	Value
Publication number	US-9703914-B2
Application number	US-201615187856-A
Country	US
Kind code	B2
Filing date	Jun 21, 2016
Priority date	Mar 24, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.

First claim

What is claimed is:

1. A method, executed by one or more processors, for optimizing placement of a logic network, the method comprising:
determining, by the one or more processors, a resource for placement and a desired location for the resource;
reserving, by the one or more processors, via a placement memory, a plurality of potential locations for the logic element that are proximate to the desired location;
determining, by the one or more processors, a best location from the plurality of potential locations; and
placing, by the one or more processors, the logic element at the best location.

2. The method of claim 1 , wherein reserving a potential location of the plurality of potential locations comprises inserting a thread identifier within at least one entry of an owning thread array stored within the placement memory.

3. The method of claim 1 , wherein reserving a potential location of the plurality of potential locations comprises inserting at least one bit within a reserved locations bitmap stored within the placement memory.

4. The method of claim 1 , wherein reserving a potential location of the plurality of potential locations comprises locking and unlocking at least a portion of the placement memory.

5. The method of claim 1 , freeing, by the one or more processors, a placement location for a deleted logic element via the placement memory.

6. The method of claim 1 , reserving, by the one or more processors, a placement location for an added logic element via the placement memory.

7. The method of claim 1 , wherein the logic element is within a logic partition that corresponds to a placement optimization thread.

8. The method of claim 1 , further comprising releasing, by the one or more processors, each of the plurality of potential locations that are not the best location.

9. A computer program product for optimizing placement of a logic network, the computer program product comprising:
at least one computer readable storage medium that is not a transitory signal per se and program instructions stored on the at least one computer readable storage medium, the program instructions comprising instructions to perform operations comprising:
determining a resource for placement and a desired location for the resource;
reserving, via a placement memory, a plurality of potential locations for the logic element that are proximate to the desired location;
determining a best location from the plurality of potential locations; and
placing the logic element at the best location.

10. The computer program product of claim 9 , wherein reserving a potential location of the plurality of potential locations comprises inserting a thread identifier within at least one entry of an owning thread array stored within the placement memory.

11. The computer program product of claim 9 , wherein reserving a potential location of the plurality of potential locations comprises inserting at least one bit within a reserved locations bitmap stored within the placement memory.

12. The computer program product of claim 9 , wherein reserving a potential location of the plurality of potential locations comprises locking and unlocking at least a portion of the placement memory.

13. The computer program product of claim 9 , wherein the operations further comprise freeing a placement location for a deleted logic element via the placement memory.

14. The computer program product of claim 9 , wherein the operations further comprise reserving a placement location for an added logic element via the placement memory.

15. The computer program product of claim 9 , wherein the operations further comprise releasing each of the plurality of potential locations that are not the best location.

16. A computer system for optimizing placement of a logic network, the computer system comprising:
one or more computers;
at least one computer readable storage medium that is not a transitory signal per se and program instructions stored on the at least one computer readable storage medium, the program instructions comprising instructions to perform operations comprising:

determining a resource for placement and a desired location for the resource;
reserving, via a placement memory, a plurality of potential locations for the logic element that are proximate to the desired location;
determining a best location from the plurality of potential locations; and
placing the logic element at the best location.

17. The computer system of claim 16 , wherein reserving a potential location of the plurality of potential locations comprises inserting a thread identifier within at least one entry of an owning thread array stored within the placement memory.

18. The computer system of claim 16 , wherein reserving a potential location of the plurality of potential locations comprises inserting at least one bit within a reserved locations bitmap stored within the placement memory.

19. The computer system of claim 16 , wherein reserving a potential location of the plurality of potential locations comprises locking and unlocking at least a portion of the placement memory.

20. The computer system of claim 16 , wherein the operations further comprise freeing a placement location for a deleted logic element via the placement memory.

Assignees

• IBM

Inventors

• Hathaway David J
• Hieter Nathaniel D
• Ramji Shyam
• Suess Alexander J

Classifications

• G06F2111/02

  CAD in a network environment, e.g. collaborative CAD or distributed simulation · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F17/5022

  Physics · mapped topic

• G06F17/505

  Physics · mapped topic

• G06F2217/04

  Physics · mapped topic