Method for library having base cell and VT-related

Patent metadata

Field	Value
Publication number	US-9703911-B2
Application number	US-201514700563-A
Country	US
Kind code	B2
Filing date	Apr 30, 2015
Priority date	Apr 30, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A method includes converting a first threshold voltage related (VT-related) cell of a first standard cell library to a first modified VT-related cell. The first standard cell library includes the first VT-related cell and a first base cell. The first VT-related cell and the first base cell each include different portions of a layout design of a first standard cell corresponding to a first performance setting. The method includes generating a second standard cell library based on the first base cell and the first modified VT-related cell. The first modified VT-related cell and the first base cell each include different portions of a layout design of a second standard cell corresponding to a second performance setting. The method further includes generating a layout design for an integrated circuit based on the second standard cell library; and forming a set of masks based on the layout design.

First claim

What is claimed is:

1. A method, comprising:
converting a first threshold voltage related (VT-related) cell of a first standard cell library to a first modified VT-related cell, the first standard cell library comprising the first VT-related cell and a first base cell, the first VT-related cell and the first base cell each comprising different portions of a layout design of a first standard cell corresponding to a first performance setting, the different portions being overlaid to obtain the layout design of the first standard cell;
generating a second standard cell library based on the first base cell and the first modified VT-related cell, the first modified VT-related cell and the first base cell each comprising different portions of a layout design of a second standard cell corresponding to a second performance setting;
generating a layout design for an integrated circuit based on the second standard cell library; and
forming a set of masks based on the layout design.

2. The method of claim 1 , further comprising:
converting a plurality of VT-related cells of the first standard cell library to a first plurality of modified VT-related cells, comprising:
converting the first VT-related cell of the first standard cell library to the first modified VT-related cell, the first plurality of modified VT-related cells comprising the first modified VT-related cell; and
converting a second VT-related cell of the first standard cell library to a second modified VT-related cell, the first plurality of modified VT-related cells comprising the second modified VT-related cell; and

converting the first plurality of modified VT-related cells to a second plurality of modified VT-related cells, comprising:
restoring the second VT-related cell of the first standard cell library to replace the second modified VT-related cell,

wherein generating the second standard cell library is performed based on the second plurality of modified VT-related cells and a plurality of base cells corresponding to the plurality of VT-related cells of the first standard cell library, the plurality of base cells comprising the first base cell.

3. The method of claim 2 , further comprising:
identifying the second VT-related cell of the first standard cell library based on matching at least a portion of a cell name of the second VT-related cell with one or more predetermined strings prior to performing restoring the second VT-related cell.

4. The method of claim 2 , wherein converting the plurality of VT-related cells of the first standard cell library to the first plurality of modified VT-related cells comprises:
replacing a first sub-set of the first plurality of VT-related cells corresponding to a first transistor threshold voltage setting with a first sub-set of the first plurality of modified VT-related cells corresponding to a second transistor threshold voltage.

5. The method of claim 4 , wherein converting the plurality of VT-related cells of the first standard cell library to the first plurality of modified VT-related cells further comprises:
replacing a second sub-set of the first plurality of VT-related cells corresponding to the second transistor threshold voltage setting with a second sub-set of the first plurality of modified VT-related cells corresponding to a third transistor threshold voltage.

6. The method of claim 1 , further comprising:
identifying a second VT-related cell of the first standard cell library based on matching at least a portion of a cell name of the second VT-related cell with one or more predetermined strings,
wherein generating the second standard cell library is performed further based on the second VT-related cell and a second base cell of the first standard cell library corresponding to the second VT-related cell.

7. The method of claim 1 , wherein the first VT-related cell, the first modified VT-related cell, and the first base cell are stored in a non-transitory storage device in a manner consistent with a Graphic Database System (GDS) file format.

8. A method, comprising:
converting a first set of threshold voltage related (VT-related) cells of a first standard cell library to a first set of modified VT-related cells, the first set of VT-related cells corresponding to a first transistor threshold voltage setting, and the first set of modified VT-related cells corresponding to a second transistor threshold voltage setting;
generating a second standard cell library to include a first set of base cells of the first standard cell library and the first set of modified VT-related cells;
generating a layout design for an integrated circuit based on the second standard cell library, generating the layout design comprising overlaying a base cell of the first set of base cells and a corresponding modified VT-related cell of the first set of modified VT-related cells; and
forming a set of masks based on the layout design.

9. The method of claim 8 , further comprising:
identifying a second set of VT-related cells of the first standard cell library based on a configuration setting,
wherein generating the second standard cell library comprises causing the second standard cell library to further include the second set of VT-related cells of the first standard cell library and a second set of base cells of the first standard cell library corresponding to the second set of VT-related cells of the first standard cell library.

10. The method of claim 9 , wherein identifying the second set of VT-related cells of the first standard cell library comprises:
matching at least a portion of cell names of the second set of VT-related cells with one or more predetermined strings.

11. The method of claim 9 , further comprising:
prior to performing identifying the second set of VT-related cells of the first standard cell library:
converting the second set of VT-related cells of the first standard cell library to a second set of modified VT-related cells; and
compiling a set of temporary VT-related cells that includes the first set of modified VT-related cells and the second set of modified VT-related cells; and

after performing identifying the second set of VT-related cells of the first standard cell library:
restoring the second set of VT-related cells of the first standard cell library to replace the second set of modified VT-related cells in the set of temporary VT-related cells.

12. The method of claim 8 , further comprising:
converting a second set of VT-related cells of the first standard cell library to a second set of modified VT-related cells, the second set of VT-related cells corresponding to the second transistor threshold voltage setting, and the second set of modified VT-related cells corresponding to a third transistor threshold voltage setting,
wherein generating the second standard cell library comprises causing the second standard cell library to further include the second set of modified VT-related cells and a second set of base cells corresponding to the second set of VT-related cells of the first standard cell library.

13. The method of claim 8 , wherein the first set of base cells of the first standard cell library, the first set of VT-related cells of the first standard cell library, and the first set of modified VT-related cells are stored in a non-transitory storage device in a manner consistent with a Graphic Database System (GDS) file format.

14. A method, comprising:
converting a first standard cell library corresponding to a first performance setting to a second standard cell library corresponding to a second performance setting,
the first standard cell library comprising a first set of threshol

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Shin Yangjae

Classifications

• G06F2111/20

  Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules · CPC title

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/5068 Primary

  Physics · mapped topic

• G06F2217/02

  Physics · mapped topic