Method and apparatus of emulating interfaces using FIFOs

Patent metadata

Field	Value
Publication number	US-9703748-B2
Application number	US-201414459731-A
Country	US
Kind code	B2
Filing date	Aug 14, 2014
Priority date	Jun 6, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

First claim

What is claimed is:

1. An integrated circuit comprising:
an access port configured to couple the integrated circuit to an external device;
a first first-in, first-out memory (FIFO) coupled to receive data from the external device via the access port and further coupled to provide data to a functional unit of the integrated circuit; and
a second FIFO coupled to provide data to the external device via the access port and further coupled to receive data from the functional unit of the integrated circuit;
wherein the access port, the first FIFO, and the second FIFO comprise a communications channel configured to emulate an interface having a predefined protocol, wherein the functional unit is configured to conduct communications with the external device through the communications channel via reads from the first FIFO and writes to the second FIFO.

2. The integrated circuit as recited in claim 1 , wherein the access port is a physical access port configured to provide a hardwired connection to the external device.

3. The integrated circuit as recited in claim 1 , wherein the access port is configured to provide a wireless connection to the external device.

4. The integrated circuit as recited in claim 1 , wherein the communications channel is configured to emulate a universal serial bus (USB) port.

5. The integrated circuit as recited in claim 1 , wherein the communications channel is configured to emulated a universal asynchronous receiver transmitter (UART) interface.

6. The integrated circuit as recited in claim 1 , wherein the access port is a debug access port configured to provide a JTAG (Joint Test Action Group) interface to the integrated circuit.

7. The integrated circuit as recited in claim 6 , wherein the access port is a serial wire debug (SWD) interface.

8. The integrated circuit as recited in claim 1 , further comprising a first timer associated with the first FIFO and a second timer associated with the second FIFO, wherein the first and second timers are configured to enforce a maximum latency for the first and second FIFOs, respectively.

9. A method comprising:
conducting communications between a functional unit internal to an integrated circuit (IC) and an external device coupled to a debug access port, wherein communications are conducted through an interface emulator coupled between the debug access port and the functional unit, the interface emulator implementing a communications channel that emulates an interface having a predefined protocol, wherein conducting communications comprises:
inputting data to the functional unit from the external device via a first first-in first-out memory (FIFO) in the IC; and
outputting data from the functional unit to the external device via a second FIFO in the IC.

10. The method as recited in claim 9 , wherein the external device is coupled to the IC by a hardwired connection.

11. The method as recited in claim 9 , wherein the external device is coupled to the IC by a wireless connection.

12. The method as recited in claim 9 , further comprising first and second timers enforcing latency limits for the first and second FIFOs, respectively.

13. The method as recited in claim 9 , wherein emulating an interface having a predefined protocol comprises emulating a universal serial bus (USB) interface.

14. The method as recited in claim 9 , emulating an interface having a predefined protocol comprises emulating a universal asynchronous receiver transmitter (UART) interface.

15. An integrated circuit comprising:
a plurality of functional units;
a debug access port;
a first interface emulator coupled between the debug access port and at least one of the plurality of functional units, wherein the first interface emulator is configured to emulate an interface having a first predefined protocol, wherein the first interface emulator includes:
a first first-in, first-out memory (FIFO), wherein the one of the plurality of functional units is configured to conduct communications with an external device coupled to the debug access port via reads from and writes to the FIFO.

16. The integrated circuit as recited in claim 15 , wherein the first interface emulator includes a first pair of FIFOs including the first FIFO and a second FIFO, wherein the first FIFO is configured to act as a first input FIFO and wherein the second FIFO is configured to act as a first output FIFO, wherein the first input FIFO is configured to receive data from the external device via the debug access port, and wherein the first output FIFO is configured to provide data to the external device via the debug access port.

17. The integrated circuit as recited in claim 15 , further comprising a second interface emulator coupled between the debug access port and one or more of the plurality of functional units, wherein the second interface emulator is configured to emulate an interface having a second predefined protocol and includes a second input FIFO and a second output FIFO.

18. The integrated circuit as recited in claim 15 , wherein the debug access port is a serial wire debug port.

19. The integrated circuit as recited in claim 16 , further comprising a timing unit coupled to the first input FIFO and the first output FIFO, wherein the timing unit is configured to limit an amount of time that data is stored in the first input FIFO and the first output FIFO.

20. The integrated circuit as recited in claim 17 , wherein the first interface emulator is configured to emulate a universal serial bus (USB) interface and the second interface emulator is configured to emulate a universal asynchronous receiver transmitter (UART) interface.

Assignees

• Apple Inc

Inventors

• Smith Michael J
• De Cesare Josh P
• Tripathi Brijesh
• Iwamoto Derek
• Keil Shane J

Classifications

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/4059

  where the synchronisation uses buffers, e.g. for speed matching between buses · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/105

  where the program performs an input/output emulation function · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title