Sleep mode operation for volatile memory circuits

Patent metadata

Field	Value
Publication number	US-9703632-B2
Application number	US-201414535970-A
Country	US
Kind code	B2
Filing date	Nov 7, 2014
Priority date	Nov 7, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

Aspects of the present disclosure are directed to circuits, apparatuses and methods for operating volatile memory circuits. According to an example embodiment, an apparatus includes a volatile memory circuit and a control circuit coupled to the volatile memory circuit. The control circuit is configured to generate and store parity data for data blocks written to the volatile memory circuit. The control circuit places the volatile memory circuit in a sleep mode in response to a first control signal. In response to a second control signal, the control circuit places the volatile memory into an active mode. In further response to the second control signal the control circuit detects and corrects errors in the data blocks stored in the volatile memory using the stored parity data.

First claim

What is claimed is:

1. An apparatus, comprising:
a volatile memory circuit; and
a control circuit configured to control a sleep mode and an active mode, wherein the control circuit is arranged to:
generate and store parity data for data blocks written to the volatile memory circuit;
in response to a first control signal, place the volatile memory circuit in the sleep mode, in which a supply voltage for the volatile memory is set to a first voltage at which data blocks stored in the volatile memory circuit are subject to an introduction of errors; and
in response to a second control signal,
place the volatile memory into the active mode, and
detect and correct errors in the data blocks stored in the volatile memory using the stored parity data including:
using a first error correction code to correct errors introduced in response to the data blocks being written; and
using a second error correction code that is different than the first error correction code to correct errors introduced during the sleep mode, wherein the volatile memory circuit is placed into the active mode by setting the supply voltage for the volatile memory circuit to a second voltage sufficient to prevent errors from being introduced in data stored by the volatile memory circuit, the first voltage being lower than the second voltage and wherein the second error correction code includes a different latency and error rate than the first error correction code.

2. The apparatus of claim 1 , wherein placing of the volatile memory circuit into the active mode includes setting the supply voltage to a second voltage that is greater than the first voltage and that is sufficient to prevent errors from being introduced in data blocks stored by the volatile memory circuit.

3. The apparatus of claim 1 , further comprising, a selection circuit configured to connect a select one of a plurality of voltage sources, that is indicated by a control signal, to a supply terminal of the volatile memory circuit.

4. The apparatus of claim 1 , wherein
the parity data is configured to correct up to a first number of errors in each data block stored in the volatile memory circuit; and
a second number of errors being less the first number of errors, wherein the second number of errors are expected to be introduced in data stored by the volatile memory circuit when the supply voltage is set to the first voltage.

5. The apparatus of claim 1 , further comprising a non-volatile memory, and wherein the setting of the supply voltage to the first voltage sets the supply voltage to a level indicated in a value stored in the non-volatile memory.

6. The apparatus of claim 5 , wherein the control circuit is further configured and arranged to, in response to a number of errors detected in response to the second control signal being less than a first threshold value, decreasing the value stored in the non-volatile memory.

7. The apparatus of claim 6 , wherein the control circuit is further configured and arranged to, in response to the number of errors detected in response to the second control signal being greater than a second threshold value, increasing the value stored in the non-volatile memory.

8. The apparatus of claim 1 , wherein the parity data is stored in the volatile memory circuit, wherein the first error correction code includes a subset of the parity data used by the second error correction code.

9. The apparatus of claim 1 , further comprising a second memory circuit; and wherein the control circuit is configured to store the parity data in the second memory circuit, wherein the second error correction code includes a concatenation of two forward error correction (FEC) codes.

10. The apparatus of claim 1 , wherein the control circuit is further configured to, in response to a data block being read from the volatile memory circuit in the active mode, detect and recover from errors in the data block using the parity data, wherein the control circuit is configured to generate separate sets of parity data using the first and second error correction codes.

11. The apparatus of claim 10 , wherein:
the detection and recovery of errors by the control circuit in response to the data block being read is performed using the first error correction code configured to correct up to a first number of errors; and
the detection and recovery of errors by the control circuit in response to the second control signal is performed using the second error correction code that is different than the first error correction code and that is configured to correct up to a second number of errors that is greater than the first number of errors.

12. The apparatus of claim 11 , wherein the placing of the volatile memory into the active mode includes setting the supply voltage to a second voltage that is greater than the first voltage and that is sufficient to prevent more than the first number of errors from being introduced in data blocks stored by the volatile memory.

13. The apparatus of claim 11 , wherein:
the second error correction code uses a first number bits of the parity data for detection and recovery of errors of a data block stored in the volatile memory circuit; and
the first error correction code uses a subset of the first number of bits for detection and recovery of errors of the data block.

14. The apparatus of claim 13 , wherein
the second error correction code is concatenated code including Reed-Solomon correction code and BCH correction code; and
the first error correction code is one of Reed-Solomon correction code or BCH correction code.

15. A method, comprising:
generating and storing parity data for data blocks written to a volatile memory circuit;
in response to a first control signal, placing the volatile memory circuit in a sleep mode by setting a supply voltage for the volatile memory circuit to a first voltage at which errors are introduced in the data blocks stored by the volatile memory circuit; and
in response to a second control signal
placing the volatile memory into an active mode by setting the supply voltage for the volatile memory circuit to a second voltage sufficient to prevent errors from being introduced in data stored by the volatile memory circuit, the first voltage being lower than the second voltage, and
detecting and correcting errors in the data blocks stored in the volatile memory using the stored parity data including:
using a first error correction code to correct errors introduced in response to the data blocks being written and
using a second error correction code that is different than the first error correction code to correct errors introduced during the sleep mode, wherein the second error correction code includes a different latency and error rate than the first error correction code.

16. The method of claim 15 , wherein
the setting of the supply voltage to the first voltage sets the supply voltage to a level indicated in a value stored in a non-volatile memory; and
further comprising
decreasing the value stored in the non-volatile memory in response to a number of detected errors being less than a first threshold value, and
increasing the value stored in the non-volatile memory in response to the number of detected errors being greater than a second threshold value, increasing the value stored in the non-volatile memory.

17. The method of claim 15 , further comprising in response to a data block being read from the volatile memory in the active mode, detecting and recovering from errors in the data block using the parity data.

18. The method of cla

Assignees

• Nxp Bv
• Nxp Bv

Inventors

• Thoen Steven

Classifications

• G06F11/106 Primary

  Correcting systematically all correctable errors, i.e. scrubbing · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title