Controlling turbo mode frequency operation in a processor

Patent metadata

Field	Value
Publication number	US-9703358-B2
Application number	US-201414551204-A
Country	US
Kind code	B2
Filing date	Nov 24, 2014
Priority date	Nov 24, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

In one embodiment, a processor comprises: a first domain including a plurality of cores; a second domain including at least one graphics engine; and a power controller including a first logic to receive a first performance request from a driver of the second domain and to determine a maximum operating frequency for the first domain responsive to the first performance request. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a first domain including a plurality of cores;
a second domain including at least one graphics engine; and
a power controller including a first logic to receive a first performance request from a driver of the second domain and to determine a maximum operating frequency for the first domain responsive to the first performance request and without reference to historical usage information of the first domain or the second domain, wherein:
when the first performance request is for a turbo mode frequency for the second domain, the first logic is to limit the maximum operating frequency for the first domain to a guaranteed operating frequency for the first domain, the guaranteed operating frequency a highest operating frequency that can be requested an operating system (OS);
when the first performance request is for a frequency less than the turbo mode frequency and above an efficient operating frequency for the second domain, the efficient operating frequency less than a guaranteed operating frequency for the second domain, the first logic is to enable the maximum operating frequency for the first domain to be above the guaranteed operating frequency for the first domain; and
when the first performance request is for a frequency less than the efficient operating frequency, the first logic is to enable the maximum operating frequency to be a maximum turbo mode frequency for the first domain.

2. The processor of claim 1 , wherein the power controller further includes a second logic to receive from the first logic the maximum operating frequency for the first domain and to determine an operating frequency for the first domain based at least in part on the maximum operating frequency and one or more constraint indications.

3. The processor of claim 2 , wherein the second logic is to determine the operating frequency for the first domain to be less than the maximum operating frequency received from the first logic responsive to the one or more constraint indications.

4. The processor of claim 2 , wherein the power controller further includes a third logic to determine the operating frequency for the first domain further based on an operating system-requested performance state for the first domain.

5. The processor of claim 1 , further comprising a first configuration register including a first field to store the first performance request, wherein the first logic is to obtain the first performance request from the first field of the first configuration register.

6. The processor of claim 1 , wherein the power controller is to enable the second domain to operate at a first turbo mode frequency responsive to the first performance request, and to thereafter enable the first domain to operate at a second turbo mode frequency responsive to a second performance request from the second domain driver, the second performance request for less than the efficient operating frequency, wherein the guaranteed operating frequency is less than the second turbo mode frequency.

7. A non-transitory machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising: receiving, in a power controller of a processor, a performance request for a second domain of the processor from a driver of the second domain, the second domain including at least one graphics engine; determining a level of the performance request;
if the level of the performance request for the second domain is a turbo mode frequency level for the second domain, the turbo mode frequency level for the second domain greater than a guaranteed frequency level for the second domain, limiting a maximum operating frequency for a first domain of the processor to a guaranteed frequency for the first domain, the first domain including at least one core;
if the level of the performance request for the second domain is less than an efficient frequency level for the second domain, the efficient frequency level for the second domain less than the guaranteed frequency level for the second domain, enabling the maximum operating frequency for the first domain to be a maximum turbo mode frequency for the first domain;
and if the level of the performance request for the second domain is greater than the efficient frequency level for the second domain and less than the turbo mode frequency level for the second domain, limiting the maximum operating frequency for the first domain to a minimal turbo mode frequency for the first domain, the minimal turbo mode frequency for the first domain greater than the guaranteed frequency for the first domain.

8. The non-transitory machine-readable medium of claim 7 , wherein the method further comprises: enabling one of the first domain and the second domain to operate at a turbo mode frequency and then causing the one of the first domain and the second domain to operate at less than the turbo mode frequency; and thereafter enabling the other of the first domain and the second domain to operate at a second turbo mode frequency.

9. The non-transitory machine-readable medium of claim 8 , wherein the method further comprises: preventing the first domain and the second domain from concurrently operating at the turbo mode frequency and the second turbo mode frequency.

10. A system comprising: a processor including a first domain having at least one core, a second domain having at least one graphics engine, and a power controller including a control logic to limit a maximum operating frequency of the at least one core to a guaranteed frequency of the at least one core when the at least one graphics engine is to be requested by a driver of the second domain to operate at a turbo mode frequency of the at least one graphics engine and without reference to historical usage information of the at least one core or the at least one graphics engine, wherein the control logic is to:
limit the maximum operating frequency of the at least one core to a first turbo mode frequency when the at least one graphics engine is to be requested to operate at less than the turbo mode frequency of the at least one graphics engine, the first turbo mode frequency of the at least one core greater than a guaranteed frequency of the at least one core and less than a maximum turbo mode frequency of the at least one core;
enable the maximum operating frequency of the at least one core to be the maximum turbo mode frequency of the at least one core when the at least one graphics engine is to be requested to operate at less than an efficient frequency of the at least one graphics engine, the efficient frequency of the at least one graphics engine less than a guaranteed frequency of the at least one graphics engine; and
limit the maximum operating frequency of the at least one core to the guaranteed frequency of the at least one core when the at least one graphics engine is to be requested to operate at the turbo mode frequency of the at least one graphics engine; and
a dynamic random access memory (DRAM) coupled to the processor.

11. The system of claim 10 , further comprising a first configuration register to store a turbo mode request from the driver of the second domain, wherein the driver of the second domain is to execute on the at least one core.

12. The system of claim 10 , wherein the control logic is further to limit the maximum operating frequency of the at least one core responsive to at least one of a power constraint and a thermal constraint on the processor.

13. The system of claim 12 , wherein the control logic is to select a performance state for the at leas

Assignees

• Intel Corp

Inventors

• Kumar Anil K

Classifications

• G06F1/3228

  Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title