Combined neutron and gamma-ray detector and coincidence test method

US9702988B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9702988-B1
Application numberUS-201614989590-A
CountryUS
Kind codeB1
Filing dateJan 6, 2016
Priority dateJan 6, 2016
Publication dateJul 11, 2017
Grant dateJul 11, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method for detecting both gamma-ray events and neutron events with a common detector, where the detector includes a layer of semiconductor material adjacent one side of a glass plate and a Gd layer on an opposite side of the glass plate, between the glass plate and a layer of silicon PIN material to form an assembly that is bounded by electrodes, including a semiconductor anode on one side of the semiconductor layer, a cathode connected to the glass plate, and a Si PIN anode on a side of the Si PIN layer opposite the semiconductor anode. The method includes the steps of: (1) monitoring the electrical signal at each of the semiconductor anode and the Si PIN anode, and (2) comparing signals from the semiconductor anode and the SI PIN anode to differentiate between gamma-ray events and neutron events based on predetermined criteria.

First claim

Opening claim text (preview).

The invention claimed is: 1. A detector for both gamma-rays and neutrons, comprising: a semiconductor layer including a semiconductor material suitable for capturing gamma-rays; a glass plate in contact with the semiconductor layer; a gadolonium (Gd) converter layer in contact with the glass plate opposite the semiconductor layer for capturing neutrons; a layer of silicon PIN (p-type/intrinsic/n-type) material of suitable thickness in contact with the Gd converter layer opposite the glass plate to detect electrons produced by neutrons captured in the Gd converter layer; a cathode contact in electrical contact with the glass plate; a first anode contact in contact with the semiconductor layer; a second anode contact in contact with the silicon PIN layer; and a processor in electric contact with the first and second anode contacts, the processor being configured to cooperate with the anode contacts and the cathode contacts to establish electric fields across the semiconductor layer and the Si PIN layer, and being configured to differentiate between signals generated by a neutron event and signals generated by a gamma-ray event. 2. A detector as set forth in claim 1 , where the semiconductor material includes any of cadmium-zinc-telluride (CdZnTe), high-resistivity gallium arsenide (GaAs), and high purity germanium (HPGe). 3. A detector as set forth in claim 1 , further comprising a printed circuit board (PCB) in electrical contact with respective ones of the first and second anode contacts to connect the first and second anode contacts to respective contacts in respective processors. 4. A plurality of adjacent spaced-apart detectors as set forth in claim 3 , with a plurality of detectors sharing common PCBs. 5. A detector as set forth in claim 1 , where the first and second anode contacts are divided into an array of pixels. 6. An array of detectors as set forth in claim 1 . 7. A detector as set forth in claim 1 , where the semiconductor layer includes cadmium-zinc-telluride (CdZnTe) and is separated into pixels aligned with pixels in the Si PIN layer. 8. A detector as set forth in claim 1 , where the semiconductor layer has a thickness of 0.35 cm, the glass plate has a thickness of at least 300 μm, the Gd layer has a thickness of 5 μm, and the Si PIN layer has a thickness of 280 μm. 9. A detector as set forth in claim 1 , where the semiconductor layer has a thickness of 1.0 cm or 1.5 cm or 2.0 cm. 10. A controller for use with a common detector for both gamma-rays and neutrons including a semiconductor layer including a semiconductor material suitable for capturing gamma-rays, a glass plate in contact with the semiconductor layer, a gadolonium (Gd) converter layer in contact with the glass plate opposite the semiconductor layer for capturing neutrons, a layer of silicon PIN (p-type/intrinsic/n-type) material of suitable thickness in contact with the Gd converter layer opposite the glass plate for detecting electrons produced from a neutron captured in the Gd converter layer, a cathode contact in electrical contact with the glass plate, a first anode contact in contact with the semiconductor layer, and a second anode contact in contact with the silicon PIN layer, the controller comprising: a processor configured to cooperate with the first anode, the second anode and the cathode to establish an electric field across the semiconductor layer and the silicon PIN layer; and the processor is configured to differentiate between signals generated by a neutron event and signals generated by a gamma-ray event as a function of coincidence testing of signals received from each of the first and second anodes. 11. A method for detecting both gamma-ray events and neutron events with a common detector, the detector including a layer of semiconductor material adjacent a glass plate, a gadolinium (Gd) converter layer adjacent an opposite side of the glass plate, and a layer of silicon PIN material in contact with the Gd converter layer on an opposite side of the glass plate to form a subassembly that is bounded by electrodes, including a semiconductor anode on one side of the semiconductor layer, a cathode connected to the glass plate, and a Si PIN cathode on a side of the Si PIN layer opposite the semiconductor anode, the method comprising the steps of: monitoring the electrical signal at each of the semiconductor anode and the Si PIN cathode; and comparing signals from the semiconductor anode and the Si PIN cathode to differentiate between gamma-ray events and neutron events based on predetermined criteria. 12. A method as set forth in claim 11 , comprising the step of establishing an electric field within the semiconductor layer and the Si PIN layer. 13. A method as set forth in claim 11 , including the step of providing a common gamma-ray and neutron detector with a controller connected to the first and second anodes and the cathode, the controller including a processor and a memory. 14. A detector for both gamma rays and neutrons, comprising: means for capturing gamma-rays that produces an electron; means for capturing neutrons that produces an electron; means for separating electrons generated by the means for capturing gamma rays from the means from electrons generated by the means for capturing neutrons; means for establishing an electric field across the means for capturing neutrons and the means for capturing gamma rays; and means for differentiating between signals generated by a neutron event and signals generated by a gamma-ray event. 15. A detector as set forth in claim 14 , where the means for capturing gamma-rays includes a semiconductor layer having a semiconductor material suitable for capturing gamma-rays. 16. A detector as set forth in claim 15 , where the means for capturing gamma-rays includes a layer of crystallized cadmium-zinc-telluride (CdZnTe) (CZT). 17. A detector as set forth in claim 14 , where the means for capturing neutrons that produces an electron includes a gadolonium (Gd) converter layer for capturing neutrons and producing an electron and a layer of silicon PIN (p-type/intrinsic/n-type) material of suitable thickness in contact with the Gd converter layer for detecting the electron. 18. A detector as set forth in claim 14 , where the means for separating electrons generated by the means for capturing gamma rays from electrons generated by the means for capturing neutrons includes a glass plate. 19. A detector as set forth in claim 14 , where the means for applying an electric field across the means for capturing neutrons and the means for capturing gamma rays includes: a cathode contact in electrical contact with the separating means; a first anode contact in contact with the gamma-ray capturing means; a second anode contact in contact with the neutron capturing means; and a processor in electric contact with the first and second anode contacts, the processor being configured to cooperate with the first and second anode contacts and the cathode contacts to establish an electric field across the means for capturing neutrons and the means for capturing gamma rays. 20. A detector as set forth in claim 14 , where the means for differentiating between signals generated by a neutron event and signals generated by a gamma-ray event includes a processor in electric contact with the means for establishing an electric field across the means for capturing neutrons and the means for capturing gamma rays, the processor being configured to differentiate between signals generated by a neutron event

Assignees

Inventors

Classifications

  • G01T3/08Primary

    with semiconductor detectors · CPC title

  • with semiconductor detectors · CPC title

  • Detector read-out circuitry (for processing gain or off-set correction H04N) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9702988B1 cover?
A method for detecting both gamma-ray events and neutron events with a common detector, where the detector includes a layer of semiconductor material adjacent one side of a glass plate and a Gd layer on an opposite side of the glass plate, between the glass plate and a layer of silicon PIN material to form an assembly that is bounded by electrodes, including a semiconductor anode on one side of…
Who is the assignee on this patent?
Raytheon Co
What technology area does this patent fall under?
Primary CPC classification G01T3/08. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 11 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).