Method and apparatus for single chamber treatment

Patent metadata

Field	Value
Publication number	US-9702042-B1
Application number	US-201615352917-A
Country	US
Kind code	B1
Filing date	Nov 16, 2016
Priority date	Apr 15, 2016
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many include forming a via to expose several layers of a microchip. The layers may include, pattered dielectric layer, a capping layer, a first metal layer and an insulator. A surface modification step is then implemented to modify and/or densify the treated surfaces of the dielectric surface. A metal compound removal step is then implemented to remove metal compounds from the bottom of the via. Finally, the via is filled with a conductive material. The surface modification and the metal compound removal steps are implemented in one chamber.

First claim

What is claimed is:

1. An apparatus for forming a microchip stack having one or more interconnects, the process chamber comprising:
a first chamber to receive to receive an insulator layer having a cavity therein;
a first processing unit cooperative with the first chamber, the first processing unit configured to:
form a first liner layer on the insulator layer to substantially cover the cavity;
form a first metal layer over the liner layer;
form a dielectric capping layer over the first metal layer and a portion of the insulator layer;
form a dielectric layer over the dielectric capping layer;
form both a line and a via through a region of the dielectric layer and extend the via to expose a portion of the dielectric capping layer and a portion of the first metal layer, the via configured to receive an interconnect layer;
surface treat the line and the via, the surface treatment including treatment with one or more of Si, NH 3 , N 2 , P, B and O 2 and including thermal treatment and direct plasma treatment performed with electrical bias in the rage of 100˜800 W;
selectively remove one or more metal compounds from a portion of the via adjacent the first metal layer to thereby expose a first area on the first metal layer, wherein one or more of H 2 , He is used to remove one or more metal compounds performed under an electrical bias of less than 100 W;
deposit a second liner layer over the surface treated via and the first area; and
fill the via with a conductive material to form the interconnect;
wherein at least the steps of surface treating the patterned dielectric surface and removing one or more metal compounds are conducted at the first chamber and wherein the first metal layer and the conductive material comprise Cu, and

wherein the dielectric surface densifies the treated surface and changes the treated dielectric surface from hydrophobic to hydrophilic.

Assignees

• IBM

Inventors

• Yang Chih-Chao
• Edelstein Daniel Charles

Classifications

• H10P72/0431

  Apparatus for thermal treatment · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title