Method of manufacturing semiconductor chip, semiconductor chip, and semiconductor device
US-2015130028-A1 · May 14, 2015 · US
Etching method, method of manufacturing article, and etching solution
US9701902B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9701902-B2 |
| Application number | US-201514845818-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 4, 2015 |
| Priority date | Sep 11, 2014 |
| Publication date | Jul 11, 2017 |
| Grant date | Jul 11, 2017 |
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- Title
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Abstract
Official abstract text for this publication.
An etching method according to an embodiment includes forming a catalyst layer made of a noble metal on a structure made of a semiconductor, and dipping the structure in an etching solution containing hydrofluoric acid, an oxidizer, and an organic additive to remove a portion of the structure that is in contact with the catalyst layer.
First claim
Opening claim text (preview).
What is claimed is: 1. An etching method, comprising: forming a catalyst layer made of a noble metal on a structure made of a semiconductor; and dipping the structure in an etching solution containing hydrofluoric acid, an oxidizer, and an organic additive to remove a portion of the structure that is in contact with the catalyst layer, the organic additive is at least one selected from the group consisting of a polyethylene glycol, succinic acid, malic acid, dipropylamine and alanine. 2. The method according to claim 1 , wherein the organic additive has a molecular weight of 60 to 20,000. 3. The method according to claim 1 , wherein a concentration of the organic additive in the etching solution is 0.01 to 1 mass %. 4. The method according to claim 1 , wherein a concentration of hydrogen fluoride in the etching solution is 5 to 10 mol/L. 5. The method according to claim 1 , wherein a concentration of the oxidizer in the etching solution is 2 to 4 mol/L. 6. The method according to claim 1 , wherein an aggregate of particles each made of the noble metal is formed as the catalyst layer, and the structure is dipped in the etching solution to remove portions of the structure that are close to the particles and a portion of the structure that corresponds to a gaps between the particles. 7. A method of manufacturing an article, the method comprising etching the structure by the etching method according to claim 1 . 8. The method according to claim 7 , wherein the article is a semiconductor device.
Assignees
Inventors
Classifications
Cutting or separating of wafers, substrates or parts of devices · CPC title
Chemical etching · CPC title
- H10P50/644Primary
Anisotropic liquid etching (H10P50/61 takes precedence) · CPC title
Electricity · mapped topic
- C09K13/08Primary
containing a fluorine compound · CPC title
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Frequently asked questions
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- What does patent US9701902B2 cover?
- An etching method according to an embodiment includes forming a catalyst layer made of a noble metal on a structure made of a semiconductor, and dipping the structure in an etching solution containing hydrofluoric acid, an oxidizer, and an organic additive to remove a portion of the structure that is in contact with the catalyst layer.
- Who is the assignee on this patent?
- Toshiba Kk
- What technology area does this patent fall under?
- Primary CPC classification H10P50/644. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jul 11 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).