Electrical charge balancing method and apparatus for functional stimulation using precision pulse width compensation

US9700724B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9700724-B2
Application numberUS-201514833115-A
CountryUS
Kind codeB2
Filing dateAug 23, 2015
Priority dateFeb 26, 2013
Publication dateJul 11, 2017
Grant dateJul 11, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An apparatus and method for electrical charge balancing when generating a stimulus during functional neural stimulation is presented. A stimulus pulse is generated (cathodic or anodic), and after a selected delay a charge compensating pulse is generated of an opposite polarity. The electrode circuit discontinuously examines electrode voltage after termination of the stimulus pulse, and utilizes this voltage to determine how long to extend the width of the charge compensating pulse. The electrode circuit thus performs accurate electrical charge cancellation to remove residual charges from the electrode by precisely controlling pulse width for an opposing polarity compensating pulse that need not have the same current level as the stimulus pulse.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus for electrical charge balancing when generating functional neural stimulation, comprising: (a) one or more stimulus electrodes; (b) a stimulation pulse generation circuit having a current sink and a current source, with said stimulation pulse generation circuit configured for directly driving current waveforms, without passing through a blocking capacitor, as a bi-phasic stimulus having both a cathodic and anodic phase through a single stimulus electrode within said one or more stimulus electrodes; (c) a switching circuit configured for sampling electrode voltage from each said stimulus electrode when each bi-phasic stimulus terminates with residual voltage sampled before the next stimulus pulse begins; (d) a feedback sensor coupled to said switching circuit for generating triggering signals in response to comparing electrode voltage sampled by said switching circuit with a reference; and (e) a digital control circuit coupled to said switching circuit and configured for receiving said feedback sensor triggering signals from said feedback sensor, said digital control circuit is configured for performing steps comprising: (i) causing said stimulation pulse generation circuit to output a bi-phasic stimulus having a first phase pulse as either a cathodic or anodic stimulus pulse; (ii) causing said stimulation pulse generation circuit to generate a second phase pulse as an opposing polarity pulse after a selected delay from said first phase pulse; (iii) adjusting pulse width of said first phase pulse and/or second phase pulse based on measured charge imbalance from residual charge measurements on a previous bi-phasic stimulus toward achieving a zero net charge residual based on input from said triggering signals to provide an equal electrical charge in each stimulation phase; and (iv) detecting stimulation charge imbalance by directly measuring electrode residual voltage from said stimulus electrode, without using a voltage measurement resistor across which voltage is sensed. 2. The apparatus recited in claim 1 , wherein said one or more stimulus electrodes comprises an array of electrodes. 3. The apparatus recited in claim 1 , wherein said switching circuit is configured for turning on and off a switch to discontinuously connect voltage from the stimulation electrode to said feedback sensor when each stimulus pulse terminates. 4. The apparatus recited in claim 1 , wherein said feedback sensor comprises a multiple-bit analog-to-digital converter (ADC). 5. The apparatus recited in claim 1 , wherein said feedback sensor comprises a comparator. 6. The apparatus recited in claim 1 , wherein said feedback sensor generates a trigger to said digital control circuit in response to comparing stimulation electrode voltage with a reference voltage to control the output of said stimulation pulse generation circuit. 7. The apparatus recited in claim 6 , wherein if a positive residual voltage is larger than a positive reference voltage, then width of cathodic current in said opposing polarity pulse is increased, or alternatively width of anodic current in said opposing polarity pulse is decreased. 8. The apparatus recited in claim 6 , wherein if a negative residual voltage is less than a negative reference voltage, then width of cathodic current in said opposing polarity pulse is increased, or alternatively width of anodic current in said opposing polarity pulse is decreased. 9. The apparatus recited in claim 1 , further comprising a digital clock circuit coupled to said digital control circuit which is configured to control the width of said first phase pulse and/or second phase pulse in response to a count of periods from said digital clock circuit, toward providing precision pulse width compensation. 10. The apparatus recited in claim 1 , wherein digital control circuit is configured to allow a selection of different stimulation waveforms. 11. The apparatus recited in claim 1 , wherein said digital control circuit is configured for generating said first phase pulse and/or second phase pulse with an adjustable width, whereby said control circuit does not require matching opposing pulse amplitudes toward achieving charge-balanced electrical stimulation. 12. The apparatus recited in claim 1 , wherein said digital control circuit is configured for generating said first phase pulse and/or second phase pulse with an adjustable width to arrive at a zero net charge residual, whereby said control circuit does not insert extra pulses, beyond said opposing polarity pulse, to achieve zero net charge residual, as these extra pulses can cause false depolarization of neural membranes. 13. The apparatus recited in claim 1 , wherein said stimulus electrodes are directly coupled to said stimulation pulse generation circuit, and thus do not incorporate a DC-blocking capacitor in series with each stimulus electrode to reduce DC current. 14. The apparatus recited in claim 1 , wherein said digital control circuit is configured for generating said first phase pulse and/or second phase pulse having pulse widths to arrive at a zero net charge residual, whereby stimulus and said opposing polarity pulse are not limited to having matched cathodic and anodic current. 15. The apparatus recited in claim 14 , wherein said digital control circuit is configured for generating said stimulus and said opposing polarity pulse which differ to support generation of electrode stimulation patterns having unmatched cathodic and anodic current intensity. 16. The apparatus recited in claim 1 , wherein said apparatus is configured for integration within a biomedical implantable functional or neural stimulation device. 17. The apparatus recited in claim 1 , wherein said apparatus is configured for integration within a biomedical implant device selected from the group of implant devices consisting of cochlear implants, retinal prosthesis, cortical stimulators and deep brain stimulators. 18. A method for electrical charge balancing of functional neural stimulation, comprising: (a) generating a bi-phasic stimulus pulse in response to current sinking and current sourcing so that said bi-phasic stimulus pulse has both a cathodic and anodic phase; (b) coupling said bi-phasic stimulus pulse directly to a single stimulus electrode, without passing through a blocking capacitor; (c) examining electrode voltage discontinuously by turning on/off a switch for sampling electrode voltage when each bi-phasic stimulus terminates with residual voltage sampled before the next stimulus pulse begins; (d) comparing the electrode voltage being sampled against a reference voltage to trigger a digital control circuit; and (e) changing pulse width of said first phase pulse and/or second phase pulse based on measured charge imbalance from residual charge measurements on a previous bi-phasic stimulus, configured for charge compensation of said stimulus pulse, in response to comparing said sampled voltage with said reference voltage to provide an equal electrical charge in each stimulation phase; and (f) detecting stimulation charge imbalance by directly measuring electrode residual voltage, without using a voltage measurement resistor across which voltage is sensed. 19. The method recited in claim 18 , wherein comparing of the electrode voltage is performed utilizing a multiple-bit analog-to-digital converter (ADC) or a comparator.

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9700724B2 cover?
An apparatus and method for electrical charge balancing when generating a stimulus during functional neural stimulation is presented. A stimulus pulse is generated (cathodic or anodic), and after a selected delay a charge compensating pulse is generated of an opposite polarity. The electrode circuit discontinuously examines electrode voltage after termination of the stimulus pulse, and utilizes…
Who is the assignee on this patent?
Univ California
What technology area does this patent fall under?
Primary CPC classification A61N1/36157. Mapped technology areas include Human Necessities.
When was this patent published?
Publication date Tue Jul 11 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).