Component-embedded board and communication terminal device

US9699908B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9699908-B2
Application numberUS-201514627194-A
CountryUS
Kind codeB2
Filing dateFeb 20, 2015
Priority dateOct 31, 2012
Publication dateJul 4, 2017
Grant dateJul 4, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A component-embedded board includes a multilayer board obtained by stacking resin layers and an electronic component in the multilayer board having terminal electrodes on at least one principal face. The resin layers include a first resin layer having a space to accommodate the electronic component and at least one first interlayer connector formed by solidifying a conductive paste outside each of at least three sides of a principal face of the electronic component and a second resin layer having second and third interlayer connectors formed by solidifying a conductive paste. At least one second interlayer connector is positioned outside the three sides of the principal face. The third interlayer connectors are joined to the terminal electrodes. The first resin layer and the second resin layer are adjacent to each other in a stacking direction within the multilayer board. The first interlayer connector and the second interlayer connector are joined.

First claim

Opening claim text (preview).

What is claimed is: 1. A component-embedded board, comprising: a multilayer board obtained by stacking a plurality of resin layers; and an electronic component provided in the multilayer board and having a plurality of terminal electrodes on at least one principal face, wherein, the resin layers at least include: a first resin layer having a space formed to accommodate the electronic component and being provided with at least one first interlayer connector outside each of at least three sides of a principal face of the electronic component, the first interlayer connector being formed by solidifying a conductive paste; and a second resin layer at least with second and third interlayer connectors, each being formed by solidifying a conductive paste such that at least one second interlayer connector is positioned outside each of the at least three sides of the principal face, and the third interlayer connectors are joined directly to the terminal electrodes, the first resin layer and the second resin layer are adjacent to each other in a stacking direction within the multilayer board, the first interlayer connector and the second interlayer connector are joined directly to each other, a material of the first interlayer connector, a material of the second interlayer connector, and a material of the third interlayer connector are the same, and the first interlayer connector and the second interlayer connector increase in diameter toward an interface between the first resin layer and the second resin layer. 2. The component-embedded board according to claim 1 , wherein the third interlayer connector has a smaller diameter at a surface of the third interlayer connector joined to one of the terminal electrodes than a diameter of the first interlayer connector at a surface of the first interlayer connector joined to the second interlayer connector. 3. The component-embedded board according to claim 1 , wherein the first interlayer connector, the second interlayer connector, and the third interlayer connector are electrically continuous to one another. 4. The component-embedded board according to claim 1 , wherein both the first and second interlayer connectors are provided in plurality outside each of the three sides. 5. The component-embedded board according to claim 1 , wherein both the first and second interlayer connectors are provided in plurality outside each of four sides of a principal face of the electronic component so as to surround the principal face when viewed in a plan view in a normal direction to the principal face. 6. The component-embedded board according to claim 1 , wherein alloy layers are formed at joints between the terminal electrodes and the third interlayer connectors during production. 7. The component-embedded board according to claim 1 , wherein the first interlayer connector and the second interlayer connector are shaped so as to be approximately symmetrical to each other with respect to the interface between the first resin layer and the second resin layer. 8. The component-embedded board according to claim 1 , wherein another electronic component is mounted on a surface of the multilayer board. 9. The component-embedded board according to claim 1 , wherein the resin layers are made of a thermoplastic material. 10. A communication terminal device comprising a component-embedded board of claim 1 . 11. The component-embedded board according to claim 1 , wherein no pattern conductor is provided between the first interlayer connector and the second interlayer connector or between the third interlayer connectors and the plurality of terminal electrodes. 12. The component-embedded board according to claim 1 , wherein the first interlayer connector and the second interlayer connector are connected not via any pattern conductors. 13. The component-embedded board according to claim 2 , wherein both the first and second interlayer connectors are provided in plurality outside each of the three sides. 14. The component-embedded board according to claim 2 , wherein both the first and second interlayer connectors are provided in plurality outside each of four sides of a principal face of the electronic component so as to surround the principal face when viewed in a plan view in a normal direction to the principal face. 15. The component-embedded board according to claim 3 , wherein the second interlayer connector and the third interlayer connector are connected via only one pattern conductor. 16. The component-embedded board according to claim 3 , wherein both the first and second interlayer connectors are provided in plurality outside each of the three sides. 17. The component-embedded board according to claim 3 , wherein both the first and second interlayer connectors are provided in plurality outside each of four sides of a principal face of the electronic component so as to surround the principal face when viewed in a plan view in a normal direction to the principal face. 18. The component-embedded board according to claim 4 , wherein both the first and second interlayer connectors are provided in plurality outside each of four sides of a principal face of the electronic component so as to surround the principal face when viewed in a plan view in a normal direction to the principal face. 19. The component-embedded board according to claim 15 , wherein both the first and second interlayer connectors are provided in plurality outside each of the three sides. 20. The component-embedded board according to claim 15 , wherein both the first and second interlayer connectors are provided in plurality outside each of four sides of a principal face of the electronic component so as to surround the principal face when viewed in a plan view in a normal direction to the principal face.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • on encapsulations · CPC title

  • On different surfaces · CPC title

  • Bond pads specially adapted therefor · CPC title

  • Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

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What does patent US9699908B2 cover?
A component-embedded board includes a multilayer board obtained by stacking resin layers and an electronic component in the multilayer board having terminal electrodes on at least one principal face. The resin layers include a first resin layer having a space to accommodate the electronic component and at least one first interlayer connector formed by solidifying a conductive paste outside each…
Who is the assignee on this patent?
Murata Manufacturing Co
What technology area does this patent fall under?
Primary CPC classification H10W70/09. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 04 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).