Substrate and method for mounting semiconductor package

Patent metadata

Field	Value
Publication number	US-9699891-B2
Application number	US-201213428375-A
Country	US
Kind code	B2
Filing date	Mar 23, 2012
Priority date	Sep 25, 2009
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A substrate includes a join-structure including a semiconductor package, first electrode pad, bump, second electrode pad, and circuit substrate joined in the order named. The substrate also includes a first wire and a second wire formed in a region below a corner of the semiconductor package. The first and second wires are configured to detect a change in electrical resistance value when the first wire or the second wire is disconnected. One of the first and second wires is connected to the first electrode pad or the second electrode pad. A break strength of each of the first wire and the second wire is lower than a break strength of the join-structure.

First claim

What is claimed is:

1. A substrate comprising:
a join-structure including a semiconductor package, first electrode pad, bump, second electrode pad, and circuit substrate joined in the order named; and
a first wire and a second wire formed in a region below a corner of the semiconductor package, each of the first wire and the second wire having a low-strength structure,
wherein:
one of the first wire and the second wire is connected to the first electrode pad or the second electrode pad, and the one of the first wire and the second wire is connected to a bump and a first measurement circuit for measuring a connection,
the other of the first wire and the second wire is not connected to any of the first electrode pad and the second electrode pad and the other of the first wire and the second wire is connected to a circuit substrate and a second measurement circuit that measures another connection across the other of the first wire and the second wire, and
a break strength of each of the first wire and the second wire is lower than a break strength of the join-structure between the circuit substrate and the semiconductor package.

2. The substrate according to claim 1 ,
wherein the first measurement circuit is configured to measure a first electrical resistance value of the first wire, and output a first disconnection signal representing disconnection of the first wire, if the first electrical resistance value exceeds a predetermined threshold value; and
wherein the second measurement circuit is configured to measure a second electrical resistance value of the second wire, and output a second disconnection signal representing disconnection of the second wire, if the second electrical resistance value exceeds the predetermined threshold value,
wherein the first disconnection signal or the second disconnection signal is used in failure prediction.

3. The substrate according to claim 1 , further comprising a prediction circuit configured to perform failure prediction by using the first disconnection signal and the second disconnection signal.

4. A substrate comprising:
a join-structure including a semiconductor chip, semiconductor package, first electrode pad, bump, second electrode pad, and circuit substrate joined in the order named; and
a first wire and a second wire formed in a region of the semiconductor package below a corner of the semiconductor chip, each of the first wire and the second wire having a low-strength structure,
wherein:
one of the first wire and the second wire is connected to the first electrode pad and/or the second electrode pad and the one of the first wire and the second wire is connected to a bump and to a first measurement circuit for measuring a connection,
the other of the first and the second wire is not connected to any of the first electrode pad and the second electrode pad and the other of the first and the second wire is connected to a circuit substrate and a second measurement circuit that measures another connection across the other of the first wire and the second wire, and
a break strength of each of the first wire and the second wire is lower than a break strength of the join-structure between the semiconductor package and the semiconductor chip.

5. A method of predicting a failure of a substrate, the substrate including a join-structure, first wire, first measurement circuit, second wire, and second measurement circuit, the join-structure including a semiconductor package, first electrode pad, bump, second electrode pad, and circuit substrate joined in the order named, the first wire being connected to the first electrode pad or the second electrode pad, and formed in a region below a corner of the semiconductor package, the first measurement circuit being connected to the first wire and configured to measure a first electrical resistance value of the first wire, the second wire not being connected to any of the first electrode pad and the second electrode pad and being formed in the region below the corner of the semiconductor package, the second measurement circuit being connected to the second wire and configured to measure a second electrical resistance value of the second wire, and wherein a break strength of each of the first wire and the second wire is lower than a break strength of the join-structure, the method comprising:
measuring the first electrical resistance value by the first measurement circuit; and
measuring the second electrical resistance value by the second measurement circuit, wherein the first electrical resistance value or the second electrical resistance value is used to predict a failure of the substrate.

6. The method according to claim 5 , further comprising:
outputting, by the first measurement circuit, a first disconnection signal representing disconnection of the first wire, if the first electrical resistance value exceeds a predetermined threshold value; and
outputting, by the second measurement circuit, a second disconnection signal representing disconnection of the second wire, if the second electrical resistance value exceeds a predetermined threshold value,
wherein the first disconnection signal or the second disconnection signal is used to predict a failure of the substrate.

7. The method according to claim 6 , wherein a time interval between the first disconnection signal and the second disconnection signal is used to predict a load applied to the join-structure of the substrate.

Assignees

• Yamayose Yuu
• Hirohata Kenji
• Toshiba Kk

Inventors

• Yamayose Yuu
• Hirohata Kenji

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H05K2203/175

  Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections · CPC title

• H05K2203/163

  Monitoring a manufacturing process · CPC title

• H05K2201/10734

  Ball grid array [BGA]; Bump grid array · CPC title

• H05K3/3436

  having an array of bottom contacts, e.g. pad grid array or ball grid array components · CPC title