Pipeline multiplexer loop architecture for decision feedback equalizer circuits

Patent metadata

Field	Value
Publication number	US-9699007-B2
Application number	US-201514840500-A
Country	US
Kind code	B2
Filing date	Aug 31, 2015
Priority date	Aug 31, 2015
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

Circuits, devices, methods for decision feedback equalization are described. A decision feedback circuit can include a plurality of decision feedback equalizer (DFE) branches, each DFE branch including: a pre-computation stage for generating a set of tap-adjusted inputs, each tap-adjusted input corresponding to a possible value of a previous output for the same DFE branch; and a decision feedback stage including a multiplexer circuit for selecting at least one output from the set of tap-adjusted inputs based on tap-adjusted inputs from other DFE branches. For at least a first DFE branch of the plurality of DFE branches, at least one selection line for the multiplexer circuit in the decision feedback stage of at least the first DFE branch of the plurality of DFE branches is an intermediate value from a multiplexer circuit for a second DFE branch of the plurality of DFE branches.

First claim

What is claimed is:

1. A decision feedback circuit comprising:
a plurality of decision feedback equalizer (DFE) branches, each DFE branch including:
a pre-computation stage configured to generate a set of tap-adjusted inputs, each tap-adjusted input corresponding to a possible value of a previous output for the same DFE branch; and
a decision feedback stage comprising a multiplexer circuit configured to select at least one output from the set of tap-adjusted inputs based on tap-adjusted inputs from other DFE branches;
where at least one selection input for a first multiplexer circuit in the decision feedback stage of a first DFE branch of the plurality of DFE branches is connected to an intermediate output from a second multiplexer circuit for a second DFE branch of the plurality of DFE branches, wherein the intermediate output is an output from a first multiplexer in the second DFE branch, where the output of the first multiplexer is an input to a second multiplexer in the second multiplexer circuit of the second DFE branch.

2. The decision feedback circuit of claim 1 , wherein the pre-computation stage comprises, for each of the set of tap-adjusted inputs:
a pre-computation circuit configured to adjust an input to the DFE branch by a pre-computed tap value associated with the corresponding previous output value; and
a quantizer configured to quantize an output from the pre-computation circuit into one of a set of possible output values to provide a tap-adjusted input in the set of tap-adjusted inputs.

3. The decision feedback circuit of claim 1 , wherein an output of at least one multiplexer in the decision feedback stage of the second DFE branch is an input to a second multiplexer in the decision feedback stage of the second DFE branch and is an input to the at least one selection input in the decision feedback stage of at least the first DFE branch.

4. The decision feedback circuit of claim 1 , wherein the multiplexer circuit comprises a series of multiplexers, and the intermediate output is an output of a first multiplexer in the series of multiplexers of the second DFE branch, where the output of the first multiplexer is an input to a second multiplexer in the series of multiplexers of the second DFE branch.

5. The decision feedback circuit of claim 1 , wherein the plurality of DFE branches are single-tap (1-Tap) decision feedback equalizers.

6. The decision feedback circuit of claim 1 , wherein at least one selection input in each DFE branch is connected to an intermediate value from the multiplexer circuit in a different DFE branch.

7. The decision feedback circuit of claim 1 , wherein the decision feedback circuit is a circuit having 2 N levels of quantization, where N is a positive integer.

8. The decision feedback circuit of claim 1 , wherein when the decision feedback circuit is a DFE with L levels, where L is a positive integer, a path between an input and an output of at least one decision feedback stage propagates through log 2 L MUX stages.

9. The decision feedback circuit of claim 1 , wherein when the decision feedback circuit is a DFE with L levels, where L is a positive integer, at least one decision feedback stage consists of log 2 L MUX stages.

10. The decision feedback circuit of claim 1 , wherein the intermediate output is an output of a multiplexer having input lines corresponding to a set of tap-adjusted inputs from the second DFE branch, and at least one selection input corresponding a tap-adjusted input from a third DFE branch.

11. A method for decision feedback equalization, the method comprising:
for at least a first decision feedback equalizer (DFE) branch of a plurality of DFE branches in a decision feedback circuit:
generating, with at least the first DFE branch, a set of tap-adjusted inputs, each tap-adjusted input corresponding to a possible value of a previous output for at least the first DFE branch of the plurality of DFE branches;
selecting, with a first multiplexer circuit of the first DFE branch of the plurality of DFE branches, at least one output from the set of tap-adjusted inputs based on at least one intermediate output from a second multiplexer circuit for a second DFE branch, wherein the intermediate output is an output from a first multiplexer in the second DFE branch where the output of the first multiplexer is an input to a second multiplexer in the second multiplexer circuit of the second DFE branch; and
outputting an output of the multiplexer circuit of the first DFE branch to another stage of the first DFE branch for use in the generation of an equalized signal.

12. The method of claim 11 wherein generating the set of tap-adjusting inputs comprises: for each possible output value from a set of possible output values:
adjusting an input to at least the first DFE branch of the plurality of DFE branches by a pre-computed tap value associated with the corresponding possible output value; and
quantizing the adjusted input into one of the set of possible output values to provide a tap-adjusted input in the set of tap-adjusted inputs.

13. The method of claim 11 , comprising receiving the intermediate output from the output of the first multiplexer in the second multiplexer circuit of the second DFE branch.

14. The method of claim 11 , wherein the plurality of DFE branches are single-tap (1-Tap) decision feedback equalizers.

15. The method of claim 11 comprising performing the steps of claim 11 for each branch in the plurality of DFE branches.

16. The method of claim 11 wherein the decision feedback circuit is a circuit having 2 N levels of quantization, where N is a positive integer.

17. The method of claim 11 wherein when the decision feedback circuit is a DFE with L levels, where L is a positive integer, a path between an input and an output of at least one decision feedback stage propagates through log 2 L MUX stages.

18. The method of claim 11 wherein when the decision feedback circuit is a DFE with L levels, where L is a positive integer, at least one decision feedback stage consists of log 2 L MUX stages.

19. The method of claim 11 comprising determining the intermediate output by selecting from a set of tap-adjusted inputs from the second DFE branch based on a tap-adjusted input from a third DFE branch.

20. An electronic device comprising:
a plurality of decision feedback equalizer (DFE) branches, each DFE branch including:
a pre-computation stage configured to generate a set of tap-adjusted inputs, each tap-adjusted input corresponding to a possible value of a previous output for the same DFE branch; and
a decision feedback stage comprising a multiplexer circuit configured to select at least one output from the set of tap-adjusted inputs based on tap-adjusted inputs from other DFE branches;
where at least one selection input for a first multiplexer circuit in the decision feedback stage of a first DFE branch of the plurality of DFE branches is connected to an intermediate output from a second multiplexer circuit for a second DFE branch of the plurality of DFE branches, wherein the intermediate output is an output from a first multiplexer in the second DFE branch where the output of the first multiplexer is an input to a second multiplexer in the second multiplexer circuit of the second DFE branch.

21. A decision feedback circuit comprising:
a first decision feedback equalizer (DFE) branch including:
a pre-computation stage configured to generate a set of tap-adjusted inputs, each tap-adjusted input corresponding to a po

Assignees

• Huawei Tech Co Ltd

Inventors

• Ho Huong

Classifications

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/03146 Primary

  with a recursive structure (H04L25/03127 takes precedence) · CPC title