Chopper stabilized amplifier with synchronous switched capacitor noise filtering

Patent metadata

Field	Value
Publication number	US-9698741-B2
Application number	US-201615276002-A
Country	US
Kind code	B2
Filing date	Sep 26, 2016
Priority date	Sep 14, 2015
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A chopper stabilzed amplifier with synchronous switched capacitor noise filtering is disclosed. In an exemplary embodiment, an apparatus includes a chopper amplifier having an input that receives an input signal and an output that outputs an amplified signal. The chopper amplifier includes an input chopping circuit and an output chopping circuit, where the input and output chopping circuits operate in response to a chop clock. The apparatus also includes a switched capacitor filter having an input that receives the amplified signal and an output that outputs a filtered signal. The switched capacitor filter operates in response to a filter clock. The apparatus also includes a filter timing adjuster that receives a reference voltage and adjusts a phase of the filter clock with respect to the chop clock to reduce chopper noise on that reference voltage.

First claim

What is claimed:

1. An apparatus comprising:
a chopper amplifier having an input that receives an input signal and an output that outputs an amplified signal, the chopper amplifier includes an input chopping circuit coupled to the input and an output chopping circuit coupled to the output, the input and output chopping circuits operate in response to a chop clock;
a switched capacitor filter having an input that receives the amplified signal and an output that outputs a filtered signal, the switched capacitor filter operates in response to at least one filter clock; and
a filter timing adjuster having an input to receive a reference voltage and the chop clock, and an output to output the at least one filter clock, the filter timing adjuster adjusts a phase of the at least one filter clock with respect to the chop clock.

2. The apparatus of claim 1 , wherein the filter timing adjuster generates a first filter clock (PH 1 ) and a second filter clock (PH 2 ), and wherein the filter timing adjuster adjusts a phase of the PH 1 clock and a phase of the PH 2 clock with respect to the chop clock to reduce chopper noise on the filtered signal.

3. The apparatus of claim 2 , wherein the filter timing adjuster comprises:
an offset sign detector that the receives the chop clock, and the amplified signal, and generates a polarity indicator; and
an exclusive-OR (XOR) gate that receives the chop clock and the polarity indicator and outputs a polarity phased servo clock adjusted in phase by 0 or 180 degrees to reduce chopper noise for offsets of that polarity.

4. The apparatus of claim 3 , wherein the filter timing adjuster comprises:
a chopper noise null servo that receives the polarity phased servo clock and the reference voltage and generates a delay control signal;
a voltage controlled delay that receives the chop clock and the delay control signal and generates a delayed chop clock; and
a non-overlap clock generator that receives the delayed chop clock and generates the PH 1 filter clock and the PH 2 filter clock.

5. The apparatus of claim 1 , wherein the chopper amplifier comprises a first GM stage.

6. The apparatus of claim 5 , further comprising:
a second GM stage that receives a filter output signal from the switched capacitor filter and generates a second amplified signal;
a third GM stage that receives the second amplified signal and a fourth amplified signal and generates a third amplified signal; and
a buffer stage that receives a filtered version of the third amplified signal and generates the reference voltage.

7. The apparatus of claim 6 , further comprising:
a fourth GM stage receives the input voltage and generates the fourth amplified signal.

8. The apparatus of claim 7 , further comprising:
a modified nested miller compensation circuit having a compensation input that receives the third amplified signal reference voltage and having a first compensation output that outputs a first feedback signal that is input to the switched capacitor filter, a second compensation output that outputs a second feedback signal that is input to the second GM stage, and a third compensation output that outputs a third feedback signal that is input to the third GM stage.

9. The apparatus of claim 8 , wherein the modified nested miller compensation circuit comprises:
a first capacitor connected between the compensation input and the first compensation output;
a second capacitor connected between the compensation input and the second compensation output;
a third capacitor connected between the compensation input and the third compensation output;
a fourth capacitor connected between a non-inverting input of the third GM stage and a signal ground; and
a fifth capacitor connected between an output of the first GM stage and the signal ground.

10. The apparatus of claim 1 , wherein the apparatus forms a bandgap reference voltage generator.

11. An apparatus comprising:
a chopper amplifier having an input that receives an input signal and an output that outputs an amplified signal, the chopper amplifier includes an input chopping circuit coupled to the input and an output chopping circuit coupled to the output, the input and output chopping circuits operate in response to a chop clock;
means for filtering the amplified signal to generate a filtered signal, the means for filtering operates in response to at least one filter clock; and
means for adjusting a phase of the filter clock relative to the chop clock to adjust the means for filtering.

12. The apparatus of claim 11 , wherein the means for adjusting generates a first filter clock (PH 1 ) and a second filter clock (PH 2 ), and wherein the means for adjusting adjusts a phase of the PH 1 clock and a phase of the PH 2 clock with respect to the chop clock to reduce chopper noise on the filtered signal.

13. The apparatus of claim 12 , wherein the means for adjusting comprises:
means for generating a polarity indicator from the chop clock and an amplified input signal; and
means for exclusive-ORing (XOR) the chop clock and the polarity indicator to generate a polarity phased servo clock that is adjusted in phase by either 0 or 180 degrees to reduce chopper noise for offsets of that polarity.

14. The apparatus of claim 13 , wherein the means for adjusting comprises:
means for generating a delay control signal from the polarity phased servo clock and a reference voltage;
means for generating a delayed chop clock from the chop clock and the delay control signal; and
means for generating non-overlapping versions of the PH 1 and PH 2 filter clocks from the delayed chop clock.

15. A method comprising:
amplifying an input signal using a chopper amplifier to generate an amplified signal, wherein the chopper amplifier includes an input chopping circuit coupled to receive the input signal and an output chopping circuit coupled to the output the amplified signal, the input and output chopping circuits operate in response to a chop clock;
filtering the amplified signal to generate a filtered signal, wherein the filtering is performed using at least one filter clock; and
adjusting a phase of the at least one filter clock relative to the chop clock.

16. The method of claim 15 , wherein the operation of adjusting comprises generating a first filter clock (PH 1 ) and a second filter clock (PH 2 ), and adjusting a phase of the PH 1 clock and a phase of the PH 2 clock with respect to the chop clock to reduce chopper noise on the reference voltage.

17. The method of claim 16 , wherein the operation of adjusting comprises:
generating a polarity indicator from the chop clock and an amplified input signal; and
exclusive-ORing (XOR) the chop clock and the polarity indicator to generate a polarity phased servo clock that is adjusted in phase by either 0 or 180 degrees to reduce chopper noise for offsets of that polarity.

18. The method of claim 17 , wherein the operation of adjusting comprises generating a delay control signal from the polarity phased servo clock and the reference voltage.

19. The method of claim 18 , wherein the operation of adjusting comprises generating a delayed chop clock from the chop clock and the delay control signal.

20. The method of claim 19 , wherein the operation of adjusting comprises generating non-overlapping versions of the PH 1 and PH 2 filter clocks from the delayed chop clock.

Assignees

• Ixys Corp

Inventors

• Blom Eric

Classifications

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F2203/45514

  the FBC comprising one or more switched capacitors, and being coupled between the LC and the IC · CPC title

• H03H19/004

  Switched capacitor networks · CPC title

• H03F1/26

  Modifications of amplifiers to reduce influence of noise generated by amplifying elements · CPC title

• H03F2200/171

  A filter circuit coupled to the output of an amplifier · CPC title