Compression control through power amplifier load adjustment

Patent metadata

Field	Value
Publication number	US-9698736-B2
Application number	US-201514867247-A
Country	US
Kind code	B2
Filing date	Sep 28, 2015
Priority date	Dec 30, 2014
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

Compression control through power amplifier load adjustment. A power amplifier module can include a power amplifier including a cascode transistor pair. The cascode transistor pair can include a first transistor and a second transistor. The power amplifier module can include a power amplifier bias controller including a current comparator configured to compare a first base current of the first transistor and a second base current of the second transistor to obtain a comparison value. The power amplifier module can include a saturation controller configured to supply a reference signal to an impedance matching network based on the comparison value. The impedance matching network can be configured to modify a load impedance of a load line in electrical communication with the power amplifier based at least in part on the reference signal.

First claim

What is claimed is:

1. A power amplifier module comprising:
a power amplifier including a cascode transistor pair, the cascode transistor pair including a first transistor and a second transistor;
a power amplifier bias controller including a current comparator configured to compare a first base current of the first transistor and a second base current of the second transistor to obtain a comparison value; and
a saturation controller configured to supply a reference signal to an impedance matching network based on the comparison value, the impedance matching network being configured to modify a load impedance of a load line in electrical communication with the power amplifier based at least in part on the reference signal.

2. The power amplifier module of claim 1 wherein the first transistor is a common base transistor and the second transistor is a common emitter transistor.

3. The power amplifier module of claim 1 wherein the load line is in electrical communication with an antenna and the load line is electrically located between the power amplifier and the antenna.

4. The power amplifier module of claim 1 wherein the impedance matching network is a dynamic impedance matching network.

5. The power amplifier module of claim 1 wherein the saturation controller is further configured to reduce compression of the power amplifier by modifying the load impedance of the load line.

6. The power amplifier module of claim 1 wherein the saturation controller further includes a digital-to-analog converter and a ramp generator, the ramp generator being configured to supply a count value to the digital-to-analog converter, the digital-to-analog converter being configured to generate the reference signal based at least in part on the count value.

7. The power amplifier module of claim 6 wherein the saturation controller includes a pull-down resistor in electrical communication with the power amplifier bias controller, a voltage input/output pin and a ramp clock generator, the ramp clock generator being configured to detect whether the first transistor is operating in a saturation region based on a voltage across the pull-down resistor, the voltage being based at least in part on the comparison value and, in response to detecting that the first transistor is operating in the saturation region, the ramp clock generator being configured to cause the ramp generator to modify the count value.

8. The power amplifier module of claim 6 wherein the digital-to-analog converter is further configured to generate the reference signal based at least in part on an average power tracking value, the average power tracking value being determined based on a target power signal received from a base station.

9. The power amplifier module of claim 6 wherein the saturation controller further includes a radio-frequency (RF) front end configured to receive a default data value from a saturation data pin, the count value initially corresponding to the default data value.

10. The power amplifier module of claim 9 wherein the default data value is one of a plurality of default data values, the default data value being selected based on a target voltage.

11. The power amplifier module of claim 10 wherein the target voltage is determined based at least in part on a target power signal received from a base station.

12. The power amplifier module of claim 1 further comprising a boost converter configured to regulate a supply voltage provided to the power amplifier.

13. The power amplifier module of claim 12 wherein the saturation controller is further configured to reduce compression of the power amplifier by a combination of providing a second reference signal to the boost converter to increase the supply voltage and modifying the load impedance of the load line by supplying the reference signal to the impedance matching network.

14. A transceiver comprising:
an impedance matching network configured to modify, based on a reference signal, a load impedance of a load line in electrical communication with a power amplifier and an antenna; and
a power amplifier module including the power amplifier, a power amplifier bias controller, and a saturation controller, the power amplifier including a cascode transistor pair, the cascode transistor pair including a first transistor and a second transistor, the power amplifier bias controller including a current comparator configured to compare a base current of the first transistor and a base current of the second transistor to obtain a comparison value, the saturation controller being configured to generate the reference signal based at least in part on the comparison value and to provide the reference signal to the impedance matching network.

15. The transceiver of claim 14 wherein the impedance matching network is a dynamic impedance matching network.

16. The transceiver of claim 14 wherein the saturation controller further includes a digital-to-analog converter and a ramp generator, the ramp generator being configured to supply a count value to the digital-to-analog converter, the digital-to-analog converter being configured to generate the reference signal based at least in part on the count value.

17. The transceiver of claim 16 wherein the saturation controller includes a pull-down resistor in electrical communication with the power amplifier bias controller, a voltage input/output pin and a ramp clock generator, the ramp clock generator being configured to detect whether the first transistor is operating in a saturation region based on a voltage across the pull-down resistor, the voltage being based at least in part on the comparison value and the ramp clock generator being configured to, in response to detecting that the first transistor is operating in the saturation region, cause the ramp generator to modify the count value.

18. The transceiver of claim 14 further comprising a boost converter configured to regulate a supply voltage provided to the power amplifier.

19. The transceiver of claim 14 wherein the saturation controller is further configured to reduce compression of the power amplifier by a combination of providing a second reference signal to the boost converter to increase the supply voltage and modifying the load impedance of the load line by supplying the reference signal to the impedance matching network.

20. A wireless device comprising:
an antenna configured to at least transmit a signal from a transceiver, the signal being based at least in part on a radio frequency input signal supplied to a power amplifier of the transceiver; and
the transceiver including an impedance matching network and a power amplifier module, the impedance matching network being configured to modify, based on a reference signal, a load impedance of a load line in electrical communication with the power amplifier and the antenna, the power amplifier module including the power amplifier, a power amplifier bias controller, and a saturation controller, the power amplifier including a cascode transistor pair, the cascode transistor pair including a first transistor and a second transistor, the power amplifier bias controller including a current comparator configured to compare a base current of the first transistor and a base current of the second transistor to obtain a comparison value, the saturation controller being configured to generate the reference signal based at least in part on the comparison value and to provide the reference signal to the impedance matching network.

Assignees

• Skyworks Solutions Inc

Inventors

• Ripley David Steven
• Lehtola Philip John

Classifications

• H04L25/0278

  Arrangements for impedance matching · CPC title

• H03F2200/78

  A comparator being used in a controlling circuit of an amplifier · CPC title

• H03F2200/462

  the current being sensed · CPC title

• H03F3/24

  of transmitter output stages · CPC title

• H03F3/191

  Tuned amplifiers (H03F3/193, H03F3/195 take precedence) · CPC title