Circuit for DC-DC conversion with current limitation

Patent metadata

Field	Value
Publication number	US-9698679-B2
Application number	US-201214356587-A
Country	US
Kind code	B2
Filing date	Oct 19, 2012
Priority date	Nov 7, 2011
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A circuit for DC-DC conversion with current limitation comprises a DC-DC converter ( 100 ) with a coil ( 110 ) and a controllable switch ( 120 ) that can be switched into a low-impedance and a high-impedance state, and a current limiter ( 300 a, 300 b ) for generating a control signal (I OC ) for controlling the state of the controllable switch in the DC-DC converter ( 100 ). The current limiter ( 300 a, 300 b ) is constructed such that the current (I L ) through the coil at which the current limitation takes place is nearly independent of the ratio of the on-times and off-times of the controllable switch in the DC-DC converter ( 100 ).

First claim

We claim:

1. A circuit for DC-DC conversion with current limitation, comprising:
a DC-DC converter ( 100 ) with a coil ( 110 ) and a controllable switch ( 120 ) that can be switched into a first state and a second state, wherein the controllable switch is higher-impedance in the second state than in the first state;
a switching signal generation circuit ( 200 ) for generating a switching signal (PWM) for switching the controllable switch ( 120 ); and
a current limiter ( 300 a , 300 b ) for generating a control signal (I OC ) for controlling the switching signal generation circuit ( 200 ),
wherein the switching signal generation circuit ( 200 ) is designed to generate, based on the level of the control signal (I OC ), a periodic sequence of the switching signal (PWM), which switches the controllable switch into the first and second state during a period duration of the switching signal, or to generate the switching signal (PWM) such that the controllable switch is switched into the second state during the period duration of the switching signal,
wherein the current limiter ( 300 a , 300 b ) has a signal generator circuit ( 311 ) for generating a periodic signal (I SLOPE ) and a correction circuit ( 320 , 320 a , 320 b , 320 c ) for generating a correction signal (I LC ),
wherein a measurement signal (I SENSE ), the level of which depends on the magnitude of the current (I L ) through the coil ( 110 ), can be supplied to the current limiter ( 300 a , 300 b ),
wherein the current limiter ( 300 a , 300 b ) is designed to determine a sum of a level (I SLOPE ) of the periodic signal and a level of the measurement signal (I SENSE ),
wherein the correction circuit ( 320 , 320 b , 320 c ) generates the correction signal (I LC ) based on the periodic signal (I SLOPE ) and the switching signal (PWM),
wherein the current limiter ( 300 a , 300 b ) generates the control signal (I OC ) based on the correction signal (I L ) and the sum,
wherein the correction circuit ( 320 b ) has an input terminal (E 320 b ) for application of the periodic signal (I SLOPE ) and an output terminal (A 320 b ) for outputting the correction signal (I LC ), a low-pass filter ( 10 ) and a sampling unit ( 40 ) for sampling the periodic signal (I SLOPE ),
wherein the sampling unit ( 40 ) and the low-pass filter ( 10 ) are connected between the input terminal (E 320 b ) and the output terminal (A 320 b ),
wherein the correction circuit ( 320 b ) has an additional input terminal (E 320 b ′) for application of the switching signal (PWM), and
wherein the sampling unit ( 40 ) is constructed such that the switching signal (PWM) is directly applied to the sampling unit ( 40 ) and the sampling times for sampling the periodic input signal (I SLOPE ) are determined by the switching signal (PWM).

2. The circuit according to claim 1 , wherein the current limiter ( 300 a ) comprises a summation circuit ( 312 a ) for generating a sum signal (I S1 ), and
wherein the summation circuit ( 312 a ) is designed to determine the sum and to generate the sum signal (I S1 ) based on the sum.

3. The circuit according to claim 2 , wherein the current limiter ( 300 a ) comprises an additional summation circuit ( 330 ) for generating an additional sum signal (I S2 ), and
wherein the additional summation circuit ( 330 ) is designed to determine an additional sum from a reference signal (I LS ) and the correction signal (I LC ) and to generate the additional sum signal (I S2 ) based on the additional sum.

4. The circuit according to claim 3 , wherein the current limiter ( 300 a ) comprises a comparator circuit ( 340 ) for generating the control signal (I OC ), and
wherein the comparator circuit ( 340 ) is designed to compare the sum signal (I S1 ) to the additional sum signal (I S2 ) and generate a level of the control signal (I OC ) based on the comparison.

5. The circuit according to claim 1 , wherein the current limiter ( 310 b ) comprises a summation circuit ( 312 b ) for generating a sum signal (I S1 ′), and
wherein a summation circuit ( 312 b ) is designed to determine an additional sum from the sum and the correction signal (I LC ) and to generate the sum signal (I S1 ′) based on the sum.

6. The circuit according to claim 5 , wherein the current limiter ( 300 b ) comprises a comparator circuit ( 340 ) for generating the control signal (I OC ), and
wherein the comparator circuit ( 340 ) is designed to compare the sum signal (I S1 ′) to a reference signal (I LS ) and generate a control signal (I OC ) based on the comparison.

7. The circuit according to one of claims 1 to 6 , wherein the switching signal generation circuit ( 200 ) is designed as a pulse width modulator that generates the switching signal (PWM) as a pulse-width modulated signal.

8. The circuit according to claim 1 , wherein the correction circuit ( 320 , 320 a , 320 b , 320 c ) is designed to determine a mean value of the level of the switching signal (PWM) or of a level of the periodic signal (I SLOPE ).

9. The circuit according to claim 1 , wherein the signal generator ( 311 ) generates the periodic signal (I SLOPE ) with a rising or falling edge when changing from one period to a subsequent period.

10. The circuit according to claim 9 , wherein the signal generator ( 311 ) generates a signal with a sawtooth progression, a signal with an exponential progression or a signal with a quadratic progression.

11. The circuit according to claim 1 , wherein the DC-DC converter ( 100 ) is constructed as a boost converter or a buck converter.

Assignees

• Ams Ag

Inventors

• Jessenig Thomas
• Lueger Manfred
• Halper Christian
• Bliem Peter

Classifications

• H02M2001/0019

  Electricity · mapped topic

• H02M1/32

  Means for protecting converters other than automatic disconnection · CPC title

• H02M3/156 Primary

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M3/1588

  comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence) · CPC title