Flexible LED device and method of making

Patent metadata

Field	Value
Publication number	US-9698563-B2
Application number	US-201113883354-A
Country	US
Kind code	B2
Filing date	Oct 27, 2011
Priority date	Nov 3, 2010
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

Provided is a flexible light emitting semiconductor device, such as an LED device, that includes a flexible dielectric layer having first and second major surfaces with a conductive layer on the first major surface and at least one cavity in the first major surface with a conductive layer in the cavity that supports a light emitting semiconductor device. The conductive layer in the cavity is electrically isolated from the second major surface of the dielectric layer.

First claim

What is claimed is:

1. A flexible article comprising:
a flexible polymeric dielectric layer having first and second major surfaces, the first surface having a first conductive layer thereon and having at least one cavity therein, the second major surface optionally having a second conductive layer thereon, the at least one cavity defined by one or more walls and a floor, the at least one cavity having a third conductive layer on at least a portion of its walls and floor; the third conductive layer configured to directly or indirectly support a light emitting semiconductor device,
wherein the at least one cavity contains an additional conducive material disposed on the third conductive layer, the combination of the additional conductive material and the third conductive layer having a thickness of at least 25 percent of a cavity depth of the at least one cavity,
wherein the first conductive layer is electrically conductive and the second and third conductive layers are thermally conductive, and
wherein there is no direct connection between the second major surface of the dielectric layer and the third conductive layer.

2. The article of claim 1 wherein the third conductive layer is electrically conductive and is electrically connected to the first conductive layer.

3. The article of claim 1 wherein the first electrically conductive layer comprises a circuit.

4. The article of claim 1 wherein the second major surface has a second conductive layer thereon.

5. The article of claim 4 wherein the second conductive layer is electrically conductive and comprises an electrical circuit.

6. The article of claim 4 wherein the second conductive layer comprises a thermally conductive adhesive.

7. The article of claim 1 wherein the first major surface of the dielectric layer has an array of cavities therein and at least a portion of the cavities are configured to support light emitting semiconductor devices.

8. The article of claim 1 wherein the cavity floor is comprised of a portion of the dielectric layer.

9. The article of claim 1 wherein the cavity floor is comprised of a dielectric material different from the dielectric layer material.

10. The article of claim 1 wherein the distance between the cavity floor and the second major surface is about 5% to about 75% of the thickness of the dielectric layer.

11. The article of claim 1 wherein the distance between the cavity floor and the second major surface is about 5% to about 60% of the thickness of the dielectric layer.

12. The article of claim 1 wherein the at least one cavity has walls that slope from the first major surface to the cavity floor at an angle of about 5° to about 60° as measured from the major plane of the dielectric layer.

13. The article of claim 1 wherein a light emitting semiconductor device is supported by the third conductive layer in the cavity and is selected from the group consisting of a bare die LES construction, an intermediate LES construction, and a complete packaged LES construction.

14. The article of claim 1 wherein the ratio of the footprint area of the light emitting semiconductor device to the area of the cavity floor is about 1:2 to about 1:4.

15. The article of claim 1 wherein the ratio of the footprint area of the light emitting semiconductor device to the area of the cavity floor is about 1:3.

16. The article of claim 1 wherein the combination of the third conductive layer and the additional conductive material in the cavity has a thickness of about 50 micrometers to about 100 micrometers.

17. The article of claim 1 wherein the cavity has an upper portion near the first major surface of the dielectric layer and a lower portion near the second major surface of the dielectric layer and wherein the diameter of the upper portion is greater than the diameter of the lower portion.

18. The article of claim 1 further comprising a second polymeric dielectric layer on the first conductive layer, the second polymeric dielectric layer having an opening extending therethrough such that the opening forms an upper portion of the cavity.

Assignees

• Palaniswamy Ravi
• Jesudoss Arokiaraj
• Narag Alejandro Aldrin Il Agcaoili
• White James R
• Tan Fong Liang
• Ouderkirk Andrew J
• Mooney Justine A
• Kreutter Nathan P
• Nie Qihong
• Gao Jian Xia
• 3M Innovative Properties Co

Inventors

• Palaniswamy Ravi
• Jesudoss Arokiaraj
• Narag Alejandro Aldrin Il Agcaoili
• White James R
• Tan Fong Liang
• Ouderkirk Andrew J
• Mooney Justine A
• Kreutter Nathan P
• Nie Qihong
• Gao Jian Xia

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title